H01L2224/1354

Planarity-tolerant reworkable interconnect with integrated testing

A structure includes an electrical interconnection between a first substrate including a plurality of protrusions and a second substrate including a plurality of solder bumps, the plurality of protrusions includes sharp tips that penetrate the plurality of solder bumps, and a permanent electrical interconnection is established by physical contact between the plurality of protrusions and the plurality of solder bumps including a metallurgical joint.

Semiconductor package with semiconductor die directly attached to lead frame and method

In one embodiment, a semiconductor package includes a semiconductor die having conductive pads. A lead frame is directly connected to the conductive pads using an electrochemically formed layer or a conductive adhesive layer thereby facilitating an electrical connection between the conductive pads of the semiconductor die and the lead frame without using separate wire bonds or conductive bumps.

Method of forming Cu pillar bump with non-metal sidewall spacer and metal top cap

A method of forming an integrated circuit device includes forming a conductive element over a substrate, wherein the conductive element is over an under bump metallurgy (UBM) layer, and the UBM layer comprises a first UBM layer and a second UBM layer over the first UBM layer. The method further includes etching the second UBM layer to expose a portion of the first UBM layer beyond a periphery of the conductive element. The method further includes forming a protection layer over sidewalls of the conductive element, over sidewalls of the second UBM layer and over a top surface of the first UBM layer. The method further includes etching the first UBM layer to remove a portion of the first UBM layer. The method further includes forming a cap layer over a top surface of the conductive element.