A bump structure that may be used to interconnect one substrate to another substrate is provided. A conductive pillar is formed on a first substrate such that the conductive pillar has a width different than a contact surface on a second substrate. In an embodiment the conductive pillar of the first substrate has a trapezoidal shape or a shape having tapered sidewalls, thereby providing a conductive pillar having base portion wider than a tip portion. The substrates may each be an integrated circuit die, an interposer, a printed circuit board, a high-density interconnect, or the like.

A semiconductor device is provided with a first semiconductor chip and a second semiconductor chip that are arranged so as to oppose each other. The first semiconductor chip has a first connecting portion provided in a first hole portion, and the second semiconductor chip has an electrically conductive second connecting portion that is composed of a concave metal film formed on the front surface of a second electrode portion, the side surface of a second hole portion, and the front surface of a second protective film. The first electrode portion and the second electrode portion are electrically connected via the first connecting portion and the second connecting portion.

A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.

The present disclosure relates to the field of semiconductor technology, and discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a semiconductor substrate, a metal pad, a bump, a first solder layer, a barrier layer, and a second solder layer. The metal pad is disposed on the semiconductor substrate; the bump is arranged on the metal pad; the barrier layer is configured on the side of the bump away from the metal pad. The barrier layer includes a first surface and a second surface. The first solder layer is arranged between the bump and the first surface of the barrier layer. The second solder layer is configured on the second surface of the barrier layer. Since the first solder layer and the second solder layer are formed by reflowed and melt solder at a high temperature and can be stretched, the height of the second solder can be adjusted automatically, which reduces the non-wetting problem caused by the package substrate deformation after reflow.

A semiconductor device is provided with a first semiconductor chip and a second semiconductor chip that are arranged so as to oppose each other. The first semiconductor chip has a first connecting portion provided in a first hole portion, and the second semiconductor chip has an electrically conductive second connecting portion that is composed of a concave metal film formed on the front surface of a second electrode portion, the side surface of a second hole portion, and the front surface of a second protective film. The first electrode portion and the second electrode portion are electrically connected via the first connecting portion and the second connecting portion.

The disclosed semiconductor structure includes a semiconductor substrate, a metal pad, a bump, a first solder layer, a barrier layer, and a second solder layer. The metal pad is disposed on the semiconductor substrate; the bump is arranged on the metal pad; the barrier layer is configured on the side of the bump away from the metal pad. The barrier layer includes a first surface and a second surface. The first solder layer is arranged between the bump and the first surface of the barrier layer. The second solder layer is configured on the second surface of the barrier layer. Since the first solder layer and the second solder layer are formed by reflowed and melt solder at a high temperature and can be stretched, the height of the second solder can be adjusted automatically, which reduces the non-wetting problem caused by the package substrate deformation after reflow.

A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.

A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.

A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.

An adhesive composition containing an adhesive component, in which the adhesive component contains a polyorganosiloxane component that is cured by hydrosilylation reaction, and the polyorganosiloxane component contains a polymer represented by formula (V) below, wherein n represents the number of repeating units, and is a positive integer, and the polyorganosiloxane component has a weight average molecular weight of 60,000 or more.

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