A method of fabricating a bridged multi-chip assembly structure includes providing a carrier substrate. The method further includes arranging a plurality of chips on the carrier substrate in a predetermined layout. Each chip has a front surface including a set of terminals formed thereon. The method further includes depositing a molding material between the plurality of chips and on the carrier substrate. The method further includes removing the carrier substrate from the plurality of chips fixed by the molding material. The method further includes bonding a bridge chip to corresponding sets of terminals of at least two chips of the plurality of chips fixed by the molding material.

A display device including: a substrate including pixel electrodes; a passivation layer on the substrate, a groove in the passivation layer between the pixel electrodes;

contact electrodes on the pixel electrodes; and a light-emitting element layer comprising a plurality of light-emitting elements respectively bonded onto the contact electrodes and having a plurality of semiconductor layers thereon. The groove does not overlap the plurality of light-emitting elements.

A semiconductor package includes a semiconductor package includes first, second, third and fourth semiconductor chips sequentially stacked on one another. Each of the first, second, third and fourth semiconductor chips includes a first group of bonding pads and a second group of bonding pads alternately arranged in a first direction and input/output (I/O) circuitry selectively connected to the first group of bonding pads respectively. Each of the first, second and third semiconductor chips includes a first group of through electrodes electrically connected to the first group of bonding pads and a second group of through electrodes electrically connected to the second group of bonding pads.

A display device and method for fabrication thereof includes a plurality of pixel electrodes and common electrode connection parts that are spaced from each other on a first substrate, a plurality of light emitting elements on the plurality of pixel electrodes, a plurality of common electrode elements on the common electrode connection parts, and a common electrode layer on the plurality of light emitting elements and the plurality of common electrode elements, wherein each of the plurality of light emitting element includes a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, each of the plurality of common electrode elements includes at least the second semiconductor layer, and the common electrode layer includes a same material as the second semiconductor layer to be connected to the second semiconductor layers of the plurality of light emitting elements.

A mounting structure includes: a first substrate that has a first surface on which a functional element is provided; a wiring portion that is provided at a position, which is different from a position of the functional element on the first surface, and is conductively connected to the functional element; a second substrate that has a second surface that is opposite to the first surface; and a conduction portion that is provided on the second surface, is connected to the wiring portion, and is conductively connected the functional element. The shortest distance between the functional element and the second substrate is longer than the longest distance between the second substrate and a position where the wiring portion is connected to the conduction portion.

In embodiments, a semiconductor package may include a first die and a second die. The package may additionally include a serializer/deserializer (SerDes) die coupled with the first and the second dies. The SerDes die may be configured to serialize signals transmitted from the first die to the second die, and deserialize signals received from the second die. Other embodiments may be described and/or claimed.

A white light emitting device, including a circuit board; a plurality of light sources mounted on the circuit board, each light source of the plurality of light sources configured to emit monochromatic light; a light converter spaced apart from the circuit board, the light converter configured to convert the monochromatic light emitted from the light sources to white light; and a compensator provided between the circuit board and the light converter, the compensator configured to convert the emitted monochromatic light to white light.

A multi-chip package including a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first side having a first conductive layer, a second side having a second conductive layer, and an edge, the first conductive layer coupled to the second conductive layer at a location adjacent to the edge. The second integrated circuit is coupled to the second conductive layer of the first integrated circuit.

Disclosed is a flip-chip device. The flip-chip device includes a die having a plurality of under bump metallizations (UBMs); and a package substrate having a plurality of bond pads. The plurality of UBMs include a first set of UBMs having a first size and a first minimum pitch and a second set of UBMs having a second size and a second minimum pitch. The first set of UBMs and the second set of UBMs are each electrically coupled to the package substrate by a bond-on-pad connection.

A semiconductor package includes a package substrate, a semiconductor chip, connection pins and a molding member. The package substrate includes wiring patterns provided respectively in insulation layers, and has insertion holes extending from an upper surface of the package substrate in a thickness direction that expose portions of the wiring patterns in different insulation layers. The semiconductor chip is disposed on the package substrate, and has a first surface on which chip pads are formed. The connection pins are provided on the chip pads, respectively, and extend through corresponding ones of the insertion holes and electrically connect to the portions of the wiring patterns, respectively, that are exposed by the insertion holes. The molding member is provided on the package substrate to cover the semiconductor chip.