A chip on film package is disclosed, including a flexible film and a chip. The flexible film includes a film base, a patterned metal layer includes a plurality of pads and disposed on an upper surface of the film base, and a dummy metal layer covering a lower surface of the film base and capable of dissipating heat of the chip. The dummy metal layer comprises at least one opening exposing the second surface, and at least one of the plurality of pads is located within the at least one opening in a bottom view of the chip on film package. The chip is mounted on the plurality of pads of the patterned metal layer.

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.

A semiconductor device includes a semiconductor element layer including a semiconductor substrate including a bump area and a dummy bump area. A TSV structure is in the bump area and vertically extends through the semiconductor substrate, a first topmost line is in the bump area and on the TSV structure and electrically connected to the TSV structure, a signal bump is in the bump area and has a first width in a first direction and is electrically connected to the TSV structure via the first topmost line, a second topmost line is in the dummy bump area and has the same vertical level as a vertical level of the first topmost line and extends in the first direction, and a dummy bump is in the dummy bump area and contacts the second topmost line and has a second width in the first direction larger than the first width.

A semiconductor device package structure is provided. The semiconductor device package structure includes a substrate having a first layer over a second layer. The first layer may have greater thermal conductivity than the second layer. The semiconductor device package structure further includes one or more dies coupled to the substrate. A heat spreader may have a first section coupled to a first surface of a first die of the one or more dies, and a second section coupled to the first layer.

The disclosure provides an electronic device which includes a substrate structure, a driving component, and a conductive pattern. The driving component and the conductive pattern are formed on the substrate structure, and the thickness of the conductive pattern is greater than or equal to 0.5 μm and less than or equal to 15 μm.

An integrated circuit (IC) package comprises a substrate comprising a dielectric and a thermal conduit that is embedded within the dielectric. The thermal conduit has a length that extends laterally within the dielectric from a first end to a second end. An IC die is thermally coupled to the first end of the thermal conduit. The IC die comprises an interconnect that is coupled to the first end of the thermal conduit. An integrated heat spreader comprises a lid over the IC die and at least one sidewall extending from the edge of the lid to the substrate that is thermally coupled to the second end of the thermal conduit.

A semiconductor device includes a semiconductor substrate divided into a pad region and a cell region and having an active surface and an inactive surface opposite to the active surface, a plurality of metal lines on the active surface of the semiconductor substrate, passivation layers on the active surface of the semiconductor substrate, and a plurality of bumps in the cell region. The passivation layers include a first passivation layer covering the plurality of metal lines and having a non-planarized top surface along an arrangement profile of the plurality of metal lines, and a second passivation layer on the non-planarized top surface of the first passivation layer and having a planarized top surface on which the plurality of bumps are disposed.

A method is disclosed for mounting and cooling a circuit component having aplurality of contacts. The method comprises mounting the circuit component on a rigid substrate of a thermally conductive and electrically insulating material with a circuit board arranged between the circuit component and the substrate. The circuit board, which has a flexible base and carries conductive traces that terminate in contact pads, is secured to the rigid substrate with at least some of the contact pads on the circuit board disposed on the side of the circuit board facing the rigid substrate, at least some of the latter contact pads being bonded to the substrate. To establish both an electrical and a thermal connection between the contacts of the circuit component and the contact pads bonded to the substrate, blind holes are formed in the flexible base of the circuit board, each hole terminating at a respective one of the contact pads bonded to the substrate. The side of the contact pads exposed by the holes is plated to form conductive vias that fill the holes and that are soldered to the contacts of the circuit component.

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.

A semiconductor device includes a substrate, a circuit element disposed on or above the upper surface of the substrate, an electrode disposed on or above the upper surface of the substrate and connected to the circuit element, and a conductor pillar bump for external connection which is disposed on the substrate and electrically connected to the electrode or the circuit element. The substrate includes a first base and a second base disposed on the first base. The circuit element and the electrode are disposed on the second base. The first base has lower thermal resistance than the second base.