A semiconductor package includes an insulating layer including a first face and a second face opposite each other, a redistribution pattern including a wiring region and a via region in the insulating layer, the wiring region being on the via region, and a first semiconductor chip connected to the redistribution pattern. The first semiconductor chip may be on the redistribution pattern. An upper face of the wiring region may be coplanar with the first face of the insulating layer.

A method includes placing a package component over a carrier, encapsulating the package component in an encapsulant, and forming a connection structure over and electrically coupling to the package component. The formation of the connection structure includes forming a first via group over and electrically coupling to the package component, forming a first conductive trace over and contacting the first via group, forming a second via group overlying and contacting the first conductive trace, wherein each of the first via group and the second via group comprises a plurality of vias, forming a second conductive trace over and contacting the second via group, forming a top via overlying and contacting the second conductive trace, and forming an Under-Bump-Metallurgy (UBM) over and contacting the top via.

A display device includes a first electrode and a second electrode disposed on a substrate and spaced apart from each other, a light emitting element on the substrate and having a first end and a second end, a third electrode disposed on the light emitting element, and electrically connecting the first electrode with the first end of the light emitting element, an insulating pattern disposed on the third electrode and exposing the second end of the light emitting element, and a fourth electrode on the substrate, and electrically connecting the second electrode with the second end of the light emitting element. A void may be formed between the light emitting element and the insulating pattern.

A package structure and method of forming the same are provided. The package structure includes a first die and a second die disposed side by side, a first encapsulant laterally encapsulating the first and second dies, a bridge die disposed over and connected to the first and second dies, and a second encapsulant. The bridge die includes a semiconductor substrate, a conductive via and an encapsulant layer. The semiconductor substrate has a through substrate via embedded therein. The conductive via is disposed over a back side of the semiconductor substrate and electrically connected to the through substrate via. The encapsulant layer is disposed over the back side of the semiconductor substrate and laterally encapsulates the conductive via. The second encapsulant is disposed over the first encapsulant and laterally encapsulates the bridge die.

A method includes placing a package component over a carrier, encapsulating the package component in an encapsulant, and forming a connection structure over and electrically coupling to the package component. The formation of the connection structure includes forming a first via group over and electrically coupling to the package component, forming a first conductive trace over and contacting the first via group, forming a second via group overlying and contacting the first conductive trace, wherein each of the first via group and the second via group comprises a plurality of vias, forming a second conductive trace over and contacting the second via group, forming a top via overlying and contacting the second conductive trace, and forming an Under-Bump-Metallurgy (UBM) over and contacting the top via.

The present disclosure relates to an LED display device, and more particularly, to an LED display device including a repair structure for a deteriorated pixel. In the present disclosure, a sub LED electrically coupled to first and second connecting electrodes for applying a voltage to a LED is disposed on a deteriorated LED. Thus, deterioration of a display quality due to a deteriorated pixel is prevented. Since it is not required to remove a deteriorated LED, a fabrication cost is reduced and a process efficiency is improved.

A semiconductor package includes a semiconductor die having an active surface and a bottom surface opposite to the active surface; a plurality of bond pads distributed on the active surface of the semiconductor die; an encapsulant covering the active surface of the semiconductor die, wherein the encapsulant comprises a bottom surface that is flush with the bottom surface of the semiconductor; and a plurality of printed interconnect features embedded in the encapsulant for electrically connecting the plurality of bond pads. Each of the printed interconnect features comprises a conductive wire and a conductive pad being integral with the conductive wire.

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die, and a redistribution structure disposed on the first semiconductor die and the insulating encapsulation. The first semiconductor die includes a first contact region and a first non-contact region in proximity to the first contact region. The first semiconductor die includes a first electrical connector disposed on the first contact region and a first dummy conductor disposed on the first non-contact region, and the first electrical connector is electrically connected to a first integrated circuit (IC) component in the first semiconductor die. The first electrical connector is electrically connected to the redistribution structure, and the first dummy conductor is electrically insulated from the first IC component in the first semiconductor die and the redistribution structure.

A semiconductor package includes an insulating layer including a first face and a second face opposite each other, a redistribution pattern including a wiring region and a via region in the insulating layer, the wiring region being on the via region, and a first semiconductor chip connected to the redistribution pattern. The first semiconductor chip may be on the redistribution pattern. An upper face of the wiring region may be coplanar with the first face of the insulating layer.

A chip package structure includes a substrate, at least two chips, a plurality of first pads, a plurality of first micro bumps, and a bridging element. The substrate has a first surface and a second surface opposite to the first surface. The two chips are disposed on the first surface of the substrate and are horizontally adjacent to each other. Each chip has an active surface. The first pads are disposed on the active surface of each of the chips. The first micro bumps are disposed on the first pads and have the same size. The bridging element is disposed on the first micro bumps such that one of the chips is electrically connected to another of the chips through the first pads, the first micro bumps, and the bridging element.