Provided is a packaging method, including: providing a base with a groove in its surface, which includes at least one pad exposed by the groove; providing a chip having a first surface and a second surface opposite to each other, at least one conductive bump being provided on the first surface of the chip; filling a first binder in the groove; applying a second binder on the first surface of the chip and the conductive bump; and installing the chip on the base, the conductive bump passing through the first binder and the second binder to connect with the pad.

A semiconductor device with high heat dissipation efficiency includes a base structure, a semiconductor chip, a heat dissipating structure, and a package body. The semiconductor chip is disposed on the base structure and has a first surface distant from the base structure. The heat dissipating structure includes a buffer layer and a first heat spreader. The buffer layer is disposed on the first surface of the semiconductor chip and a coverage rate thereof on the first surface is at least 10%. The first heat spreader is disposed on the buffer layer and bonded to the first surface of the semiconductor chip through the buffer layer. The package body encloses the semiconductor chip and the heat dissipating structure, and the package body and the buffer layer have the same heat curing temperature.

An OLED display panel and a manufacturing method thereof, and an OLED display device are disclosed. The OLED display panel includes a base substrate; a first film layer and a second film layer, sequentially provided on the base substrate, a first via-hole penetrating through the first film layer being provided in the first film layer, a second via-hole penetrating through the second film layer being provided in the second film layer at a position corresponding to the first via-hole, the second via-hole being in communication with the first via-hole, and the first film layer and the second film layer form a first step at a position of the second via-hole; and a connection wire, provided in both the first via-hole and the second via-hole and overlying the first step.

A semiconductor device with high heat dissipation efficiency includes a base structure, a semiconductor chip, a heat dissipating structure, and a package body. The semiconductor chip is disposed on the base structure and has a first surface distant from the base structure. The heat dissipating structure includes a buffer layer and a first heat spreader. The buffer layer is disposed on the first surface of the semiconductor chip and a coverage rate thereof on the first surface is at least 10%. The first heat spreader is disposed on the buffer layer and bonded to the first surface of the semiconductor chip through the buffer layer. The package body encloses the semiconductor chip and the heat dissipating structure, and the package body and the buffer layer have the same heat curing temperature.

A light conversion device includes a light-emitting unit, a photoelectric conversion unit, and an electroconductive bonding layer. Each of the light-emitting unit and the photoelectric conversion unit includes a first-type region and a second-type region opposite to the first-type region. The electroconductive bonding layer is disposed between the light-emitting unit and the photoelectric conversion unit for connecting the photoelectric conversion unit with the light-emitting unit. When the light conversion device is operated to receive a bias and an external light, the light-emitting unit generates a modulated light having a frequency different from that of the external light.

Die-substrate assemblies having sinter-bonded backside via structures, and methods for fabricating such die-substrate assemblies, are disclosed. In embodiments, the method includes obtaining an integrated circuit (IC) die having a backside over which a backmetal layer is formed and into which a plated backside via extends. The IC die is attached to an electrically-conductive substrate by: (i) applying sinter precursor material over the backmetal layer and into the plated backside via; (ii) positioning a frontside of the electrically-conductive substrate adjacent the plated backmetal layer and in contact with the sinter precursor material; and (iii) sintering the sinter precursor material to yield a sintered bond layer attaching and electrically coupling the IC die to the frontside of the electrically-conductive substrate through the backmetal layer and through the plated backside via. The sintered bond layer contacts and is metallurgically bonded to the backside via lining.

A semiconductor device includes a semiconductor element, which has a protective film having an opening that exposes a part of a source electrode and disposed/provided to position an end portion thereof on the source electrode. A rewiring layer has wiring that is connected to the source electrode and to a conductive connecting member, and an insulator that covers a part of the source wiring. The insulator includes: an insulating film having (a) an opening for exposing a part of the source wiring, and (b) an end portion of the opening provided in a facing region of the opening; and an insulating film having (c) (i) an opening for exposing a part of the source wiring having a solder arranged therein and (ii) a connecting member arranged therein.

The present disclosure is directed to a method of manufacturing semiconductor devices that includes providing a substrate such as a leadframe having a non-etched adhesion promoter, NEAP layer over the die mounting surface and attaching thereon a semiconductor die having an attachment surface including a first and a second die areas that are wettable by electrically conductive solder material. The NEAP layer is selectively removed, e.g., via laser ablation, from the first substrate area and the second substrate area of the die mounting surface of the substrate. The first substrate area and the second substrate area of the substrate having complementary shapes with respect to the first and second die areas of the semiconductor die. Electrically conductive solder material is dispensed on the first and second substrate areas of the substrate. A semiconductor die is flipped onto the substrate with the first die area and the second die area aligned with the first substrate area and the second substrate area of the substrate having the solder material dispensed thereon. The electrically conductive solder material thus provides electrical coupling of: the first die area and the first substrate area, and the second die area and the second substrate area.

HEMT having a drain field plate is provided. The drain field plate is formed in the area between the gate and drain of a HEMT. The drain field plate includes a metal pad that has a larger projection area than the drain pad. The drain field plate and semiconductor layer disposed beneath the drain field plate form a metal-semiconductor (M-S) Schottky structure. The capacitance of the M-S Schottky structure generates capacitance in the semiconductor area, which increases the breakdown voltage of the transistor components of the HEMT. A portion of the substrate under the active area may be removed to thereby increase the heat conductivity and reduce the junction temperature of the transistor components of the HEMT.

Structures, methods and devices are disclosed, related to improved stack structures in electronic devices. In some embodiments, a stack structure includes a pad implemented on a substrate, the pad including a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, the upper metal layer having an upper surface. In some embodiments, the stack structure also includes a passivation layer implemented over the upper metal layer, the passivation layer including a pattern configured to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface, the pattern defining a plurality of openings to expose the upper surface of the upper metal layer.