Patent classifications
H01L2224/35831
Semiconductor Device and Method of Forming Clip Bond Having Multiple Bond Line Thicknesses
A semiconductor device has a leadframe and a first electrical component disposed over the leadframe. A clip bond is disposed over the first electrical component. The clip bond has a plurality of recesses each having a different depth. A first recess is proximate to a first distal end of the first electrical component, and a second recess is proximate to a second distal end of the first electrical component opposite the first distal end of the first electrical component. A depth of the first recess is different from a depth of the second recess. A third recess is over a surface of the first electrical component. A depth of the third recess is different from the depth of the first recess and the depth of the second recess. A second electrical component is disposed over the leadframe. The clip bond extends over the second electrical component.
Multi-clip structure for die bonding
A multi-clip structure includes a first clip for die bonding and a second clip for die bonding. The multi-clip structure further includes a retaining tape fixed to the first clip and to the second clip to hold the first clip and the second clip together.
Multi-clip structure for die bonding
A multi-clip structure includes a first clip for die bonding and a second clip for die bonding. The multi-clip structure further includes a retaining tape fixed to the first clip and to the second clip to hold the first clip and the second clip together.
SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURE
A semiconductor device including a lead frame, a die attached to the lead frame using a first solder, and a clip attached to the die using a second solder is provided. The clip includes a notch arranged for a check of the excess of the second solder.
ELECTRICAL CONNECTION MEMBER, ELECTRICAL CONNECTION STRUCTURE, AND METHOD FOR MANUFACTURING ELECTRICAL CONNECTION MEMBER
An electrical connection member (1, 301, 401, 501, 601) includes a clad material (10, 110, 610) including at least both a first Cu layer (12) made of a Cu material and a low thermal expansion layer (11) made of an Fe material or Ni material having an average thermal expansion coefficient from room temperature to 300° C. smaller than that of the first Cu layer, the first Cu layer and the low thermal expansion layer being bonded to each other.
Porous Cu on Cu surface for semiconductor packages
A semiconductor package includes a plurality of metal leads and a semiconductor die attached to the plurality of metal leads by an interconnect. A surface of the plurality of metal leads, a metallized surface of the semiconductor die, and/or a surface of the interconnect comprises Cu and has a thermal conductivity in a range of 340 to 400 W/mK and an electrical conductivity in a range of 80 to 110% IACS. One or more of the surfaces which comprise Cu and have a thermal conductivity in the range of 340 to 400 W/mK and an electrical conductivity in the range of 80 to 110% IACS also includes micropores having a diameter in a range of 1 m to 10 m. A method of manufacturing a metal surface with such micropores also is described.
Porous Cu on Cu Surface for Semiconductor Packages
A semiconductor package includes a plurality of metal leads and a semiconductor die attached to the plurality of metal leads by an interconnect. A surface of the plurality of metal leads, a metallized surface of the semiconductor die, and/or a surface of the interconnect comprises Cu and has a thermal conductivity in a range of 340 to 400 W/mK and an electrical conductivity in a range of 80 to 110% IACS. One or more of the surfaces which comprise Cu and have a thermal conductivity in the range of 340 to 400 W/mK and an electrical conductivity in the range of 80 to 110% IACS also includes micropores having a diameter in a range of 1 m to 10 m. A method of manufacturing a metal surface with such micropores also is described.
Semiconductor Package and Related Methods
Implementations of semiconductor packages may include one or more die coupled over a substrate, an electrically conductive spacer coupled over the substrate, and a clip coupled over and to the one or more die and the electrically conductive spacer. The clip may electrically couple the one or more die and the electrically conductive spacer.
Semiconductor Package and Related Methods
Implementations of semiconductor packages may include one or more die coupled over a substrate, an electrically conductive spacer coupled over the substrate, and a clip coupled over and to the one or more die and the electrically conductive spacer. The clip may electrically couple the one or more die and the electrically conductive spacer.
Multi-Clip Structure for Die Bonding
A multi-clip structure includes a first clip for die bonding and a second clip for die bonding. The multi-clip structure further includes a retaining tape fixed to the first clip and to the second clip to hold the first clip and the second clip together.