A semiconductor module includes a first power semiconductor device, a conductive wire, and a resin film. The conductive wire is joined to a surface of a first front electrode of the first power semiconductor device. The resin film is formed to be continuous on at least one of an end portion or an end portion of a first joint between the first front electrode and the conductive wire in a longitudinal direction of the conductive wire, a surface of the first front electrode, and a surface of the conductive wire. The resin film has an elastic elongation rate of 4.5% to 10.0%.

A semiconductor module includes a first power semiconductor device, a conductive wire, and a resin film. The conductive wire is joined to a surface of a first front electrode of the first power semiconductor device. The resin film is formed to be continuous on at least one of an end portion or an end portion of a first joint between the first front electrode and the conductive wire in a longitudinal direction of the conductive wire, a surface of the first front electrode, and a surface of the conductive wire. The resin film has an elastic elongation rate of 4.5% to 10.0%.

A semiconductor device, having a substrate including an insulating plate and a circuit board provided on a front surface of the insulating plate. The circuit board has a first disposition area and a second disposition area with a gap therebetween, and a groove portion, of which a longitudinal direction is parallel to the gap, formed in the gap. The semiconductor device further includes a first semiconductor chip and a second semiconductor chip located on the circuit board in the first disposition area and the second disposition area, respectively, and a blocking member located in the gap across the groove portion in parallel to the longitudinal direction in a plan view of the semiconductor device.

A semiconductor device, having a substrate including an insulating plate and a circuit board provided on a front surface of the insulating plate. The circuit board has a first disposition area and a second disposition area with a gap therebetween, and a groove portion, of which a longitudinal direction is parallel to the gap, formed in the gap. The semiconductor device further includes a first semiconductor chip and a second semiconductor chip located on the circuit board in the first disposition area and the second disposition area, respectively, and a blocking member located in the gap across the groove portion in parallel to the longitudinal direction in a plan view of the semiconductor device.

The present invention relates to a semiconductor package in which a metal bridge, which is bent and has elasticity and a non-vertical structure, may protect a semiconductor chip in such a way that push-stress occurring while molding is relieved by being absorbed or dispersed by being diverted, a method of manufacturing the same, and the metal bridge applied to the semiconductor package.

An object of the present disclosure is to provide a high strength aluminum alloy material having a ribbon shape, which can be an alternative to copper-based materials and iron-based materials having a ribbon shape, and a conductive member, a conductive component, a spring member, a spring component, a semiconductor module member, a semiconductor module component, a structural member and a structural component including the aluminum alloy material. The aluminum alloy material of the present disclosure has an alloy composition containing Mg: 0.2% to 1.8% by mass, Si: 0.2% to 2.0% by mass, and Fe: 0.01% to 1.50% by mass, with the balance being Al and inevitable impurities, wherein the aluminum alloy material has a Vickers hardness (HV) of 90 or more and 190 or less and has a ribbon shape.

There is provided an Al bonding wire which can achieve a sufficient bonding reliability of bonded parts of the bonding wire under a high temperature state where a semiconductor device using the Al bonding wire is operated. The Al bonding wire is characterized in that the wire contains 0.02 to 1% by mass of Fe, further contains 0.05 to 0.5% by mass in total of at least one or more of Mn and Cr, and the balance includes Al and inevitable impurities, wherein a total content of Fe, Mn and Cr in solid solution is 0.01 to 1% by mass. The Al bonding wire contains Mn and Cr in addition to Fe, so that Fe, Mn and Cr can be promoted to form a solid solution in quenching treatment after the solution treatment. Accordingly, the Al bonding wire can achieve an effect of solid-solution strengthening of the wire due to the increase in the total content of Fe, Mn and Cr in solid solution and an effect of preventing recrystallization from proceeding during use of the semiconductor device at a high temperature for a long time.

There is provided a bonding wire for semiconductor devices that exhibits a favorable bondability even when being applied to wedge bonding at the room temperature, and also achieves an excellent bond reliability. The bonding wire includes a core material of Cu or Cu alloy (hereinafter referred to as a “Cu core material”), and a coating containing a noble metal formed on a surface of the Cu core material. A concentration of Cu at a surface of the wire is 30 to 80 at%.

Semiconductor chip package device and semiconductor chip package method are provided. The semiconductor chip package device includes: a lead frame, chips, an encapsulating layer, and an electroplating layer. The lead frame includes a first surface, a second surface, first grooves, second grooves, and third grooves. The first grooves are connected to the second grooves to form through holes and the third grooves disposed at ends of the lead frame. The chips are electrically connected to the lead frame. The encapsulating layer is formed by using an encapsulating material to encapsulate the chips and at least a portion of the lead frame. The first grooves are filled with the encapsulating material. The electroplating layer is disposed on the second surface of the lead frame, and extends into the third grooves or into the third grooves and the second grooves.

Semiconductor chip package device and semiconductor chip package method are provided. The semiconductor chip package device includes: a lead frame, chips, an encapsulating layer, and an electroplating layer. The lead frame includes a first surface, a second surface, first grooves, second grooves, and third grooves. The first grooves are connected to the second grooves to form through holes and the third grooves disposed at ends of the lead frame. The chips are electrically connected to the lead frame. The encapsulating layer is formed by using an encapsulating material to encapsulate the chips and at least a portion of the lead frame. The first grooves are filled with the encapsulating material. The electroplating layer is disposed on the second surface of the lead frame, and extends into the third grooves or into the third grooves and the second grooves.