One aspect relates to a method of manufacture of an electronic assembly comprising at least these steps: providing a substrate having at least a first contact area; positioning a spot of a UV curable substance on the substrate; positioning an electrically conductive item on the substrate wherein the electrically conductive item is superimposed on the first contact area and on the spot of curable substance; exposing the UV curable substance to UV irradiation, wherein a mechanical connection between the electrically conductive item and substrate is formed; and optionally connecting the first contact area with the electrically conductive item. One aspect relates to an electronic assembly comprising a substrate with a contact area, a spot of a cured substance on the substrate and an electrically conductive item that is in electrically conductive connection with the first contact area and mechanically connected through the spot of cured substance to the substrate.

One aspect relates to a method of manufacture of an electronic assembly comprising at least these steps: providing a substrate having at least a first contact area; positioning a spot of a UV curable substance on the substrate; positioning an electrically conductive item on the substrate wherein the electrically conductive item is superimposed on the first contact area and on the spot of curable substance; exposing the UV curable substance to UV irradiation, wherein a mechanical connection between the electrically conductive item and substrate is formed; and optionally connecting the first contact area with the electrically conductive item. One aspect relates to an electronic assembly comprising a substrate with a contact area, a spot of a cured substance on the substrate and an electrically conductive item that is in electrically conductive connection with the first contact area and mechanically connected through the spot of cured substance to the substrate.

A semiconductor device includes a die pad, a bond post, a die disposed over the die pad, a wire coupled between the die and the bond post and having a first portion bonded to the die at a first bond area and a second portion bonded to the bond post at a second bond area, a first bonding cover disposed over the first portion, and a second bonding cover disposed over the second portion. A method includes bonding a first portion of a wire to a die at a first bond area, bonding a second portion of the wire to a first bond post of a lead frame at a second bond area, applying a bonding material over the first bond area to form a first bonding cover, and applying the bonding material over the second bond area to form a second bonding cover.

The present disclosure provides a semiconductor device package. The semiconductor device package includes a substrate, a first module disposed on the substrate, a second module disposed on the substrate and spaced apart from the first module, and a conductive element disposed outside of the substrate and configured to provide a signal transmission path between the first module and the second module.

A semiconductor device in which a semiconductor element mounted on a laminate substrate and an electrically conductive connection member are sealed with a sealing material, includes: a primer layer in an interface between the sealing material and sealed members including the laminate substrate, the semiconductor element, and the electrically conductive connection member, in which the sealing material includes a first sealing layer which is provided in contact with the primer layer; and a second sealing layer which covers the first sealing layer, the semiconductor device satisfies α.sub.p≥α.sub.1>α.sub.2 in which α.sub.p, α.sub.1, and α.sub.2 represent coefficients of linear thermal expansion of the primer layer, the first sealing layer, and the second sealing layer, respectively, α.sub.c≥15×10.sup.−6/° C. in which α.sub.c represents a composite coefficient of linear thermal expansion of the sealing layers, and E.sub.c≥5 GPa or more in which E.sub.c represents a composite Young's modulus of the sealing layers.

A semiconductor device in which a semiconductor element mounted on a laminate substrate and an electrically conductive connection member are sealed with a sealing material, includes: a primer layer in an interface between the sealing material and sealed members including the laminate substrate, the semiconductor element, and the electrically conductive connection member, in which the sealing material includes a first sealing layer which is provided in contact with the primer layer; and a second sealing layer which covers the first sealing layer, the semiconductor device satisfies α.sub.p≥α.sub.1>α.sub.2 in which α.sub.p, α.sub.1, and α.sub.2 represent coefficients of linear thermal expansion of the primer layer, the first sealing layer, and the second sealing layer, respectively, α.sub.c≥15×10.sup.−6/° C. in which α.sub.c represents a composite coefficient of linear thermal expansion of the sealing layers, and E.sub.c≥5 GPa or more in which E.sub.c represents a composite Young's modulus of the sealing layers.

A semiconductor device in which a semiconductor element mounted on a laminate substrate and an electrically conductive connection member are sealed with a sealing material, includes: a primer layer in an interface between the sealing material and sealed members including the laminate substrate, the semiconductor element, and the electrically conductive connection member, in which the sealing material includes a first sealing layer which is provided in contact with the primer layer; and a second sealing layer which covers the first sealing layer, the semiconductor device satisfies α.sub.p≥α.sub.1>α.sub.2 in which α.sub.p, α.sub.1, and α.sub.2 represent coefficients of linear thermal expansion of the primer layer, the first sealing layer, and the second sealing layer, respectively, α.sub.c≥15×10.sup.−6/° C. in which α.sub.c represents a composite coefficient of linear thermal expansion of the sealing layers, and E.sub.c≥5 GPa or more in which E.sub.c represents a composite Young's modulus of the sealing layers.

A semiconductor device in which a semiconductor element mounted on a laminate substrate and an electrically conductive connection member are sealed with a sealing material, includes: a primer layer in an interface between the sealing material and sealed members including the laminate substrate, the semiconductor element, and the electrically conductive connection member, in which the sealing material includes a first sealing layer which is provided in contact with the primer layer; and a second sealing layer which covers the first sealing layer, the semiconductor device satisfies α.sub.p≥α.sub.1>α.sub.2 in which α.sub.p, α.sub.1, and α.sub.2 represent coefficients of linear thermal expansion of the primer layer, the first sealing layer, and the second sealing layer, respectively, α.sub.c≥15×10.sup.−6/° C. in which α.sub.c represents a composite coefficient of linear thermal expansion of the sealing layers, and E.sub.c≥5 GPa or more in which E.sub.c represents a composite Young's modulus of the sealing layers.

A method of forming an electrical contact and a method of forming a chip package are provided. The methods may include arranging a metal contact structure including a non-noble metal and electrically contacting the chip, arranging a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

In various embodiments, a method of forming an electrical contact is provided. The method may include depositing, by atomic layer deposition, a passivation layer over at least a region of a metal surface, wherein the passivation layer may include aluminum oxide, and electrically contacting the region of the metal surface with a metal contact structure, wherein the metal contact structure may include copper.