In accordance with an embodiment, an electronic circuit includes a first transistor device, at least one second transistor device, and a drive circuit. The first transistor device is integrated in a first semiconductor body, and includes a first load pad at a first surface of the first semiconductor body and a control pad and a second load pad at a second surface of the first semiconductor body. The at least one second transistor device is integrated in a second semiconductor body, and includes a first load pad at a first surface of the second semiconductor body and a control pad and a second load pad at a second surface of the second semiconductor body. The first load pad of the first transistor device and the first load pad of the at least one second transistor device are mounted to an electrically conducting carrier.

An integrated circuit (IC) includes semiconductor substrate with a metal stack including a lower, upper and a top metal layer that includes bond pads and a detection bond pad (DBP). A wirebond damage detector (WDD) includes the DBP over a first and second connected structure. The first and second connected structures both include spaced apart top segments of the upper metal layer coupled to spaced apart bottom segments of the lower metal layer. The DBP is coupled to one end of the first connected structure, and ≥1 metal trace is coupled to another end extending beyond the DBP to a first test pad. The second connected structure includes metal traces coupled to respective ends each extending beyond the DBP to a second test pad and to a third test pad.

An integrated circuit (IC) includes semiconductor substrate with a metal stack including a lower, upper and a top metal layer that includes bond pads and a detection bond pad (DBP). A wirebond damage detector (WDD) includes the DBP over a first and second connected structure. The first and second connected structures both include spaced apart top segments of the upper metal layer coupled to spaced apart bottom segments of the lower metal layer. The DBP is coupled to one end of the first connected structure, and >1 metal trace is coupled to another end extending beyond the DBP to a first test pad. The second connected structure includes metal traces coupled to respective ends each extending beyond the DBP to a second test pad and to a third test pad.

Leadless power amplifier (PA) packages having topside termination interposer (TTI) arrangements, and associated fabrication methods, are disclosed. Embodiments of the leadless PA package include a base flange, a first set of interposer mount pads, a first RF power die, a package body. The first RF power die is attached to a die mount surface of the base flange and electrically interconnected with the first set of interposer mount pads. The TTI arrangement is electrically coupled to the first set of interposer mount pads and projects therefrom in the package height direction. The package body encloses the first RF power die and having a package topside surface opposite the lower flange surface. Topside input/output terminals of the PA package are accessible from the package topside surface and are electrically interconnected with the first RF power die through the TTI arrangement and the first set of interposer mount pads.

A power module includes a mount layer, a control layer, and a drive layer that are formed on an electrically insulative substrate and multiple power semiconductor elements mounted on the mount layer in one direction and each including a first drive electrode connected to the mount layer, a second drive electrode connected to the drive layer, and a control electrode connected to the control layer. A control terminal is connected to the control layer and a detection terminal is connected to the drive layer. At least one of the control layer and the drive layer includes a detour portion that detours to reduce a difference between the power semiconductor elements in a sum of a length of a first conductive path between the control electrode and the control terminal and a length of a second conductive path between the second drive electrode and the detection terminal.

A semiconductor chip includes a first cell row constituted by I/O cells arranged in the X direction and a second cell row constituted by I/O cells arranged in the first direction, spaced from the first cell row by a predetermined distance in the Y direction. A plurality of external connecting pads include pads each connected with any of the I/O cells and a reinforcing power supply pad that is not connected with any of the I/O cells and is connected with a pad for power supply. The reinforcing power supply pad is placed to lie in a region between the first cell row and the second cell row.

A driving chip and a display panel are provided. The display panel includes the driving chip, and a plurality of first bonding pads and a plurality of second bonding pads disposed at two opposite sides out of the driving chip. The driving chip includes a group of first input leads and a group of second input leads. There is an interval between the group of first input leads and the group of second input leads. The group of first input leads is disposed near the first bonding pads, and the group of second input leads is disposed near the second bonding pads.

A semiconductor device includes a substrate and a first conductive layer formed over a first surface of the substrate. The first conductive layer is patterned into a first portion of a first passive circuit element. The first conductive layer is patterned to include a first coiled portion. A second conductive layer is formed over a second surface of the substrate. The second conductive layer is patterned into a second portion of the first passive circuit element. The second conductive layer is patterned to include a second coiled portion exhibiting mutual inductance with the first coiled portion. A conductive via formed through the substrate is coupled between the first conductive layer and second conductive layer. A semiconductor component is disposed over the substrate and electrically coupled to the first passive circuit element. An encapsulant is deposited over the semiconductor component and substrate. The substrate is mounted to a printed circuit board.

A bidirectional switch module includes a plurality of bidirectional switches and a mount board. Each of the plurality of bidirectional switches includes a first source electrode, a first gate electrode, a second gate electrode, and a second source electrode. On the mount board, the plurality of bidirectional switches are mounted. In the bidirectional switch module, the plurality of bidirectional switches are connected in parallel.

A light emitting diode (LED) package includes a substrate having a pair of first wiring electrodes and a pair of second wiring electrodes, an LED chip on the substrate, the LED chip being electrically connected to the pair of first wiring electrodes, a wavelength conversion film on the LED chip, an electrochromic film on the wavelength conversion film, the electrochromic film electrically connected to the pair of second wiring electrodes, and the electrochromic film being configured to have a first color before application of a voltage and to be transparent after application of the voltage, an optical lens on the electrochromic film, and a lateral structure having a reflective layer covering at least a portion of a lateral surface of each of the LED chip and the wavelength conversion film, and a color layer on the reflective layer and having a second color.