Provided with a semiconductor apparatus which is able to be miniaturized and is provided with a Peltier element. The semiconductor apparatus is provided with a semiconductor substrate and the Peltier element which is disposed facing the semiconductor substrate. The Peltier element has a first substrate and a thermoelectric semiconductor which is disposed between the first substrate and the semiconductor substrate. The semiconductor substrate has a first electrode provided on a surface side facing the first substrate. The first substrate has a second electrode provided on a surface side facing the semiconductor substrate. The first electrodes and the second electrodes are each connected to the thermoelectric semiconductor.

A semiconductor package according to the inventive concept includes a first semiconductor chip configured to include a first semiconductor device, a first semiconductor substrate, a plurality of through electrodes penetrating the first semiconductor substrate, and a plurality of first chip connection pads arranged on an upper surface of the first semiconductor substrate; a plurality of second semiconductor chips sequentially stacked on an upper surface of the first semiconductor chip and configured to each include a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chip connection pads arranged on an upper surface of the second semiconductor substrate; a plurality of bonding wires configured to connect the plurality of first chip connection pads to the plurality of second chip connection pads; and a plurality of external connection terminals arranged on a lower surface of the first semiconductor chip.

A semiconductor package includes a package substrate having a first side portion adjacent to a first edge, and a second side portion adjacent to a second edge opposite the first edge; a plurality of first substrate pads on the package substrate at the first side portion of the package substrate; a first chip on the package substrate; a second chip stacked on the first chip in a step-wise manner to result in a first exposure region exposing a portion of a surface of the first chip with respect to the second chip due to the step-wise stacking, the first exposure region being adjacent to a first edge of the first chip; a plurality of first bonding pads on a first portion of the first exposure region, the first portion of the first exposure region being adjacent to the first edge of the first chip; a plurality of second bonding pads on a second portion of the first exposure region, the second portion of the first exposure region further from the first edge of the first chip than the first portion of the first exposure region is to the first edge of the first chip, the plurality of second bonding pads being electrically insulated from any circuit components in the first chip; a plurality of third bonding pads on a surface of the second chip; and a plurality of bonding wires electrically connecting the third bonding pads to the first substrate pads via the second bonding pads.

According to one embodiment, a semiconductor device includes a substrate, first stacked components, second stacked components, and a coating resin. The first stacked components include first chips and are stacked on a surface of the substrate. The second stacked components include second chips and are stacked on the surface. The coating resin covers the surface, the first stacked components, and the second stacked components. A first top surface of a second farthest one of the first chips away from the surface differs in position in a first direction from a second top surface of second farthest one of the second chips away from the surface.

A memory device might include a controller configured to cause the memory device to generate a first sum of expected peak current magnitudes for a plurality of memory devices, and generate a second sum of expected peak current magnitudes for a subset of the plurality of memory devices, if the memory device were to initiate a next phase of an access operation in a selected operating mode; to compare the first sum to a first current demand budget for the plurality of the memory devices; to compare the second sum to a second current demand budget for the subset of memory devices; and to initiate the next phase of the access operation in the selected operating mode in response to the first sum being less than or equal to the first current demand budget and the second sum being less than or equal to the second current demand budget.

A semiconductor package includes a package substrate, a first semiconductor chip and a second semiconductor chip sequentially stacked on the package substrate, the first semiconductor chip and the second semiconductor chip being disposed in a form of an offset stack structure, and the second semiconductor chip including an overhang further protruding beyond a side surface of the first semiconductor chip in a first horizontal direction, an adhesive member disposed on a lower surface of the second semiconductor chip, the adhesive member including an extension extending to a lower level than an upper surface of the first semiconductor chip. The extension contacts the side surface of the first semiconductor chip, and overlaps with at least a portion of the overhang in a vertical direction.

A semiconductor package including a substrate and at least one semiconductor chip on the substrate may be provided. The substrate may include a body layer having a top surface and a bottom surface, a first thermal conductive plate on the top surface of the body layer, the first thermal conductive plate connected to a ground terminal of the semiconductor chip, and a thermal conductive via penetrating the body layer and being in contact with the first thermal conductive plate.

A semiconductor package according to the inventive concept includes a first semiconductor chip configured to include a first semiconductor device, a first semiconductor substrate, a plurality of through electrodes penetrating the first semiconductor substrate, and a plurality of first chip connection pads arranged on an upper surface of the first semiconductor substrate; a plurality of second semiconductor chips sequentially stacked on an upper surface of the first semiconductor chip and configured to each include a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chip connection pads arranged on an upper surface of the second semiconductor substrate; a plurality of bonding wires configured to connect the plurality of first chip connection pads to the plurality of second chip connection pads; and a plurality of external connection terminals arranged on a lower surface of the first semiconductor chip.

A method of forming a flip-chip integrated circuit die that includes a front side including active circuitry formed therein and a plurality of bond pads in electrical communication with the active circuitry, at least two through-wafer vias in electrical communication with the active circuitry and extending at least partially though the die and having portions at a rear side of the die, and a bond wire external to the die and electrically coupling the portions of the at least two through-wafer vias to one another at the rear side of the die.

A semiconductor device includes a wiring substrate inside which a wiring layer is provided, a plurality of first semiconductor chips stacked in a shifted manner on the wiring substrate and each provided with a connection terminal on a surface facing the wiring substrate, and a second semiconductor chip having a function different from functions of the first semiconductor chips and provided on the wiring substrate on a side where the connection terminals are electrically connected to the wiring substrate.