A printed circuit board capable of reducing or suppressing connection failure includes a base film made of insulating material, an electric conductor pattern formed on a front surface of the base film, and an insulating cover film covering the electric conductor pattern. The printed circuit board also includes a circuit portion with a circuit formed by the electric conductor pattern, and a pad portion with a bonding pad composed of the electric conductor pattern exposed from the insulating cover film. The pad portion has higher rigidity than the circuit portion.

In a method of manufacturing a semiconductor device, a semiconductor chip has first and second pads, a passivation film formed such that respective parts of the first and second pads are exposed, a first surface-metal-layer provided on the part of the first pad and a part of the passivation film, and a second surface-metal-layer provided on the part of the second pad and another part of the passivation film. Respective wires are electrically connected to the first and second surface-metal-layers. The semiconductor chip and the respective wires are then sealed with a resin.

A semiconductor device has a first semiconductor die stacked over a second semiconductor die which is mounted to a temporary carrier. A plurality of bumps is formed over an active surface of the first semiconductor die around a perimeter of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. A plurality of conductive vias is formed through the encapsulant around the first and second semiconductor die. A portion of the encapsulant and a portion of a back surface of the first and second semiconductor die is removed. An interconnect structure is formed over the encapsulant and the back surface of the first or second semiconductor die. The interconnect structure is electrically connected to the conductive vias. The carrier is removed. A heat sink or shielding layer can be formed over the encapsulant and first semiconductor die.

A structure of a printed circuit board and a carrier is coupled with a chip, and the printed circuit board contains: a trace, and a dielectric layer. The carrier includes at least an element. The trace at least includes a terminal; the trace has an upper surface, a lower surface, and a side edge, the dielectric layer includes a predetermined opening, an upper surface, a lower surface, and a side edge, wherein the predetermined opening is formed by a portion of the dielectric layer and corresponds to the terminal of the trace. And the carrier is coupled with the dielectric layer.

A sensor package structure is provided. The sensor package structure includes a substrate, a sensor chip disposed on the substrate, a plurality of wires electrically coupling the sensor chip to the substrate, a supporting colloid layer disposed on the substrate, and a light-permeable sheet that is disposed on the supporting colloid layer. The substrate has a first board surface and a second board surface that is opposite to the first board surface. The substrate has a chip-accommodating slot recessed in the first board surface. The sensor chip is disposed in the chip-accommodating slot, and a gap distance between a top surface of the sensor chip and the first board surface is less than or equal to 10 ?m. The supporting colloid layer is ring-shaped and is disposed on the first board surface, and each of the wires is at least partially embedded in the supporting colloid layer.

An integrated circuit (IC) package includes a molding having a first surface and a second surface, the first surface opposing the second surface. An interconnect is encased in the molding. The interconnect includes pads situated at a periphery of a side of the IC package. A portion of the pads are exposed at the first surface of the molding. A die pad is situated proximal to the second surface of the molding. The die pad has a first surface and a second surface, the first surface opposing the second surface, and the second surface is circumscribed by the second surface of the molding. A die is mounted on the first surface of the die pad. A heat spreader is mounted on the second surface of the molding and the second surface of the die pad. The heat spreader extends between edges of the second surface of the molding.

Image sensor modules are provided including a lower structure, and an upper structure on the lower structure. The image sensor module further includes a semiconductor substrate in which an image sensor is formed. The lower structure includes a semiconductor chip on a region of a lower surface of the upper structure and connected to the image sensor; a reinforcing frame along an edge of the lower surface of the upper structure; and a resin molding portion between the reinforcing frame and the semiconductor chip. The reinforcing frame has a Young's modulus higher than a Young's modulus of the resin molding portion.

An integrated circuit (IC) package includes a molding having a first surface and a second surface, the first surface opposing the second surface. An interconnect is encased in the molding. The interconnect includes pads situated at a periphery of a side of the IC package. A portion of the pads are exposed at the first surface of the molding. A die pad is situated proximal to the second surface of the molding. The die pad has a first surface and a second surface, the first surface opposing the second surface, and the second surface is circumscribed by the second surface of the molding. A die is mounted on the first surface of the die pad. A heat spreader is mounted on the second surface of the molding and the second surface of the die pad. The heat spreader extends between edges of the second surface of the molding.

A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die.

A printed circuit board capable of reducing or suppressing connection failure includes a base film made of insulating material, an electric conductor pattern formed on a front surface of the base film, and an insulating cover film covering the electric conductor pattern. The printed circuit board also includes a circuit portion with a circuit formed by the electric conductor pattern, and a pad portion with a bonding pad composed of the electric conductor pattern exposed from the insulating cover film. The pad portion has higher rigidity than the circuit portion.