A semiconductor device includes: a conductive base substrate; a semiconductor chip mounted on the base substrate and having a signal pad; a frame configured to surround the semiconductor chip, to be mounted on the base substrate, and to include a step having an inner first upper surface and an outer second upper surface higher than the first upper surface in a plan view, wherein a first conductor pattern provided on the first upper surface is electrically connected to the base substrate; a capacitive component mounted on the first conductor pattern; a signal terminal mounted on the second upper surface of the frame; a first bonding wire configured to electrically connect the signal pad and an upper surface of the capacitive component; and a second bonding wire configured to electrically connect the upper surface of the capacitive component and the signal terminal.

An electronic device includes a multilevel lamination structure having a core layer, dielectric layers and conductive features formed in metal layers on or between respective ones or pairs of the dielectric layers. The core layer and the dielectric layers extend in respective planes of orthogonal first and second directions and are stacked along an orthogonal third direction. The conductive features include a first patterned conductive feature having multiple conductive turns in each of a first pair of the metal layers to form a first winding having a first turn and a final turn adjacent to one another in the same metal layer of the first pair, and a second patterned conductive feature having multiple conductive turns in a second pair of the metal layers to form a second winding having a first turn and a final turn.

A semiconductor package includes a first lead with first and second ends extending in the same direction as one another. At least one second lead has first and second ends and is partially surrounded by the first lead. A die pad is provided and a die is connected to the die pad. Wires electrically connect the die to the first lead and the at least one second lead. An insulating layer extends over the leads, the die pad, and the die such that the first end of the at least one second lead is exposed from the semiconductor package and the second end of the first lead is encapsulated entirely within the insulating layer.

An amplifier module that implements two or more amplifying units connected in series is disclosed. The amplifier module includes a package, input and output terminals, two or more amplifying units including the first unit and the final unit, an output bias terminal for supplying an output bias to one of amplifying units except for the final unit, and an input bias terminal for supplying an input bias to another one of the amplifying units except for the first unit. A feature of the amplifier module is that the output bias terminal and the input bias terminal are disposed in axial symmetry with respect to a reference axis connecting the input terminal with the output terminal in one side of the package.

A transistor package that includes a metal submount; a transistor die mounted on said metal submount; a surface mount IPD component that includes a dielectric substrate; and the dielectric substrate mounted on said metal submount. Additionally, the dielectric substrate includes one of the following: an irregular shape, a non-square shape, and a nonrectangular shape.

A packaged RF transistor amplifier includes an RF transistor amplifier die having a first terminal, a first lead, an integrated passive device that includes a first series microstrip transmission line, a first bond wire coupled between the first terminal and the first series microstrip transmission line, and a second bond wire coupled between the first series microstrip transmission line and the first lead.

An electronic device includes a magnetic assembly with a multilevel lamination or metallization structure having a core layer, dielectric layers and conductive features formed in metal layers on or between the dielectric layers in respective planes of orthogonal first and second directions and stacked along an orthogonal third direction. The conductive features include first and second patterned conductive features forming first and second windings, first and second conductive capacitor plates, and first and second conductive field plates, in which the first conductive capacitor plate is between the first conductive field plate and the core layer along the third direction and the second conductive capacitor plate is between the second conductive field plate and the core layer along the third direction.

A transistor device includes a semiconductor structure, source and drain contacts on the semiconductor structure, a gate on the semiconductor structure between the source and drain contacts, and a surface passivation layer on the semiconductor structure between the gate and the source or drain contact. The surface passivation layer includes an opening therein that exposes a first region of the semiconductor structure for processing the first region differently than a second region of the semiconductor structure adjacent the gate. Related devices and fabrication methods are also discussed.

A method of forming a high electron mobility transistor (HEMT) includes: providing a semiconductor structure comprising a channel layer and a barrier layer sequentially stacked on a substrate; forming a first insulating layer on the barrier layer; and forming a gate contact, a source contact, and a drain contact on the barrier layer. An interface between the first insulating layer and the barrier layer comprises a modified interface region on a drain access region and/or a source access region of the semiconductor structure such that a sheet resistance of the drain access region and/or the source access region is between 300 and 400 Ω/sq.

The present application describes a system in package which features no printed circuit board inside an encapsulation structure and comprises: a copper holder with a silicon layer at a top face; a plurality of dies mounted on the silicon layer and electrically connected to a plurality of data pins of the copper holder; a passive element mounted on the silicon layer and electrically connected to the dies wherein the dies are electrically connected to the ground pin of the copper holder; a molding compound encasing the dies and the passive element on the top face of the copper holder.