A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.

Stacked semiconductor devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device can include a package substrate and a stack of semiconductor dies carried by the package substrate. The stack of semiconductor dies includes a first die carried by the package substrate and a second die carried by the first die. The semiconductor device also includes an interconnect module carried by the package substrate adjacent the stack of semiconductor dies. The interconnect module includes a first end coupled the package substrate, a second end opposite the first end, a conductive via extending through a body of organic material from the first end to the second end. The first semiconductor die can is electrically coupled directly to the package substrate, while the second semiconductor die is electrically coupled to the package substrate through the second end of the interconnect module.

Stacked semiconductor devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device can include a package substrate and a stack of semiconductor dies carried by the package substrate. The stack of semiconductor dies includes a first die carried by the package substrate and a second die carried by the first die. The semiconductor device also includes an interconnect module carried by the package substrate adjacent the stack of semiconductor dies. The interconnect module includes a first end coupled the package substrate, a second end opposite the first end, a conductive via extending through a body of organic material from the first end to the second end. The first semiconductor die can is electrically coupled directly to the package substrate, while the second semiconductor die is electrically coupled to the package substrate through the second end of the interconnect module.

A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip and a connection structure. The second semiconductor chip includes a first segment that protrudes outwardly beyond one side of the first semiconductor chip and a second connection pad on a bottom surface of the first segment of the second semiconductor chip. The connection structure includes a first structure between the substrate and the first segment of the second semiconductor chip and a first columnar conductor penetrating the first structure to be in contact with the substrate and being disposed between the second connection pad and the substrate, thereby electrically connecting the second semiconductor chip to the substrate.

A semiconductor device includes a semiconductor element, at least one first resin member, and at least one conducting wire. The semiconductor element includes a front electrode and a body part. The at least one first resin member is disposed on a second surface of the front electrode. The at least one conducting wire includes a joining part. The at least one first resin member includes a convex part. The convex part protrudes from the front electrode in a direction away from the body part. The at least one conducting wire includes a concave part. The concave part is adjacent to the joining part. The concave part extends along the convex part. The concave part is fitted to the convex part.

In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

A semiconductor integrated circuit device includes first and second semiconductor chips stacked one on top of the other. First power supply lines in the first semiconductor chip are connected with second power supply lines in the second semiconductor chip through a plurality of first vias. The directions in which the first power supply lines and the second power supply lines extend are orthogonal to each other.

A wiring substrate includes a first wiring layer, a first insulation layer, and a second wiring layer. The first insulation layer covers an upper surface and a side surface of the first wiring layer and exposes a lower surface of the first wiring layer. The second wiring layer is stacked on at least one of a lower surface of the first insulation layer and the lower surface of the first wiring layer.

In one example, a semiconductor device comprises a cavity substrate comprising a base and a sidewall to define a cavity, an electronic component on a top side of the base in the cavity, a lid over the cavity and over the sidewall, and a valve to provide access to the cavity, wherein the valve has a plug to provide a seal between a cavity environment and an exterior environment outside the cavity. Other examples and related methods are also disclosed herein.

A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform.