H01L2224/48644

Apparatus and method for a component package

A component package and a method of forming are provided. A first component package may include a first semiconductor device having a pair of interposers attached thereto on opposing sides of the first semiconductor device. Each interposer may include conductive traces formed therein to provide electrical coupling to conductive features formed on the surfaces of the respective interposers. A plurality of through vias may provide for electrically connecting the interposers to one another. A first interposer may provide for electrical connections to a printed circuit board or subsequent semiconductor device. A second interposer may provide for electrical connections to a second semiconductor device and a second component package. The first and second component packages may be combined to form a Package-on-Package (“PoP”) structure.

Apparatus and method for a component package

A component package and a method of forming are provided. A first component package may include a first semiconductor device having a pair of interposers attached thereto on opposing sides of the first semiconductor device. Each interposer may include conductive traces formed therein to provide electrical coupling to conductive features formed on the surfaces of the respective interposers. A plurality of through vias may provide for electrically connecting the interposers to one another. A first interposer may provide for electrical connections to a printed circuit board or subsequent semiconductor device. A second interposer may provide for electrical connections to a second semiconductor device and a second component package. The first and second component packages may be combined to form a Package-on-Package (“PoP”) structure.

Semiconductor device and method for manufacturing the same
09768228 · 2017-09-19 · ·

The present invention relates to a semiconductor device, including: a substrate; a plurality of first semiconductor elements and a second semiconductor element arranged on a mount area of the substrate; an external electrode to supply electricity to the first and second semiconductor elements; and a frame of reflective material formed at a periphery of the mount area. Extensions of the first external electrodes are formed at the inner side of the plurality of wirings, and the first external electrodes are formed along the periphery of the mount area at the outer side of at least one of the second external electrodes or the wiring connected to the second external electrodes, and electrodes of the plurality of first semiconductor elements are electrically connected to the pair of first external electrodes by a bonding wire that bridges across at least one of the pair of the second external electrodes or the wiring electrically connected to the pair of second external electrodes with intervening a part of the frame therebetween.

Semiconductor device and method for manufacturing the same
09768228 · 2017-09-19 · ·

The present invention relates to a semiconductor device, including: a substrate; a plurality of first semiconductor elements and a second semiconductor element arranged on a mount area of the substrate; an external electrode to supply electricity to the first and second semiconductor elements; and a frame of reflective material formed at a periphery of the mount area. Extensions of the first external electrodes are formed at the inner side of the plurality of wirings, and the first external electrodes are formed along the periphery of the mount area at the outer side of at least one of the second external electrodes or the wiring connected to the second external electrodes, and electrodes of the plurality of first semiconductor elements are electrically connected to the pair of first external electrodes by a bonding wire that bridges across at least one of the pair of the second external electrodes or the wiring electrically connected to the pair of second external electrodes with intervening a part of the frame therebetween.

POWER AMPLIFIER MODULES INCLUDING SEMICONDUCTOR RESISTOR AND TANTALUM NITRIDE TERMINATED THROUGH WAFER VIA

One aspect of this disclosure is a power amplifier module that includes a power amplifier, a semiconductor resistor, a tantalum nitride terminated through wafer via, and a conductive layer electrically connected to the power amplifier. The semiconductor resistor can include a resistive layer that includes a same material as a layer of a bipolar transistor of the power amplifier. A portion of the conductive layer can be in the tantalum nitride terminated through wafer via. The conductive layer and the power amplifier can be on opposing sides of a semiconductor substrate. Other embodiments of the module are provided along with related methods and components thereof.

POWER AMPLIFIER MODULES INCLUDING SEMICONDUCTOR RESISTOR AND TANTALUM NITRIDE TERMINATED THROUGH WAFER VIA

One aspect of this disclosure is a power amplifier module that includes a power amplifier, a semiconductor resistor, a tantalum nitride terminated through wafer via, and a conductive layer electrically connected to the power amplifier. The semiconductor resistor can include a resistive layer that includes a same material as a layer of a bipolar transistor of the power amplifier. A portion of the conductive layer can be in the tantalum nitride terminated through wafer via. The conductive layer and the power amplifier can be on opposing sides of a semiconductor substrate. Other embodiments of the module are provided along with related methods and components thereof.

POP STRUCTURE OF THREE-DIMENSIONAL FAN-OUT MEMORY AND PACKAGING METHOD THEREOF
20230352450 · 2023-11-02 ·

The package-on-package (POP) structure includes a first package unit of three-dimensional fan-out memory chips and a SiP package unit of the two-dimensional fan-out peripheral circuit chip. The first package unit includes: memory chips laminated in a stepped configuration; a molded substrate; wire bonding structures; a first rewiring layer; a first encapsulating layer; and first metal bumps, formed on the first rewiring layer. The SiP package unit includes: a second rewiring layer; a peripheral circuit chip; a third rewiring layer, bonded to the circuit chip; first metal connection pillars; a second encapsulating layer for the circuit chip and the first metal connection pillars; and second metal bumps on the second rewiring layer. The first metal bumps are bonded to the third rewiring layer. Integrating the two package units into the POP is enabled by three rewiring layers and the molded substrate which supports the first package unit during wire bonding process.

Power amplifier systems with control interface and bias circuit

One aspect of this disclosure is a power amplifier system that includes a control interface, a power amplifier, a passive component, and a bias circuit. The power amplifier and the passive component can be on a first die. The bias circuit can be on a second die. The control interface can operate as a serial interface or as a general purpose input/output interface. The power amplifier can be controllable based at least partly on an output signal from the control interface. The bias circuit can generate a bias signal based at least partly on an indication of the electrical property of the passive component. Other embodiments of the system are provided along with related methods and components thereof.

Power amplifier systems with control interface and bias circuit

One aspect of this disclosure is a power amplifier system that includes a control interface, a power amplifier, a passive component, and a bias circuit. The power amplifier and the passive component can be on a first die. The bias circuit can be on a second die. The control interface can operate as a serial interface or as a general purpose input/output interface. The power amplifier can be controllable based at least partly on an output signal from the control interface. The bias circuit can generate a bias signal based at least partly on an indication of the electrical property of the passive component. Other embodiments of the system are provided along with related methods and components thereof.

Semiconductor device, electronic component and method

In an embodiment, a semiconductor device includes a galvanically isolated signal transfer coupler having a contact pad. The contact pad includes a metallic base layer, a metallic diffusion barrier layer arranged on the metallic base layer, and a metallic wire bondable layer arranged on the metallic diffusion barrier layer. The metallic diffusion barrier layer includes a first portion and a second portion. The first portion has a first surface and a second surface opposing the first surface. The first surface has a curved surface at the periphery. The first portion extends in a transverse plane and has a width. The second portion protrudes from the second surface intermediate the width of the first portion.