A semiconductor device includes first conductive films that are provided, above a semiconductor substrate, at least on both sides of a non-formation region in which the first conductive films are not provided; an interlayer dielectric film including a first portion that is provided on the non-formation region, second portions provided above the first conductive film on both sides of the non-formation region, and a step portion that connects the first portion and the second portions; a second conductive film provided above the interlayer dielectric film; through terminal portions that penetrate the second portions of the interlayer dielectric film; and a wire bonded with the second conductive film above the first portion, where the through terminal portions include one or more first through terminal portions and one or more second through terminal portions being provided at positions opposite to each other with a bonded portion of the wire being interposed therebetween.

A semiconductor device includes a substrate, a semiconductor chip, a plurality of bonding pads on a surface of the semiconductor chip, a plurality of probe pads on a surface of the semiconductor chip, a plurality of connection pads on a surface of the substrate, and a plurality of bonding wires that electrically connect the bonding pads and the connection pads. The plurality of bonding pads include a first bonding pad and a second bonding pad, the plurality of probe pads include a first probe pad and a second probe pad, and a part of the first probe pad is disposed between the second bonding pad and the second probe pad.

A semiconductor device includes: a semiconductor chip; and an Ag fired cap formed so as to cover a source pad electrode formed on the semiconductor chip. The semiconductor chip is disposed on a first substrate electrode, and one end of a Cu wire is bonded onto the Ag fired cap by means of an ultrasonic wave. There is provided a semiconductor device capable of improving a power cycle capability, and a fabrication method of such a semiconductor device.

A semiconductor device includes first conductive films that are provided, above a semiconductor substrate, at least on both sides of a non-formation region in which the first conductive films are not provided; an interlayer dielectric film including a first portion that is provided on the non-formation region, second portions provided above the first conductive film on both sides of the non-formation region, and a step portion that connects the first portion and the second portions; a second conductive film provided above the interlayer dielectric film; through terminal portions that penetrate the second portions of the interlayer dielectric film; and a wire bonded with the second conductive film above the first portion, where the through terminal portions include one or more first through terminal portions and one or more second through terminal portions being provided at positions opposite to each other with a bonded portion of the wire being interposed therebetween.

Methods, systems, and apparatuses for preventing corrosion between dissimilar bonded metals. The method includes providing a wafer having a plurality of circuits, each of the plurality of circuits having a plurality of bond pads including a first metal; applying a coating onto at least the plurality of bond pads; etching a hole in the coating on each of the plurality of bond pads to provide an exposed portion of the plurality of bond pads; dicing the wafer to separate each of the plurality of circuits; die bonding each of the plurality of circuits to a respective packaging substrate; and performing a bonding process to bond a second, dissimilar metal to the exposed portion of each of the plurality of bond pads such that the second, dissimilar metal encloses the hole in the coating of each of the plurality of bond pads, thereby enclosing the exposed portion.

In various embodiments, a chip package is provided. The chip package may include a chip including a chip metal surface, a metal contact structure electrically contacting the chip metal surface, and packaging material including a contact layer being in physical contact with the chip metal surface and/or with the metal contact structure; wherein at least in the contact layer of the packaging material, a summed concentration of chemically reactive sulfur, chemically reactive selenium and chemically reactive tellurium is less than 10 atomic parts per million.

A wire bonding method includes steps of: forming a Free Air Ball (FAB) at an end of a metal wire; pressing the FAB onto a flat surface of a workpiece to deform the FAB; contacting the deformed FAB to a metal pad, wherein the metal pad is made of a first material and the metal wire is made of a second material, and a hardness of the first material is smaller than a hardness of the second material; and bonding the deformed FAB on the metal pad.

A semiconductor device includes: a semiconductor chip; and an Ag fired cap formed so as to cover a source pad electrode formed on the semiconductor chip. The semiconductor chip is disposed on a first substrate electrode, and one end of a Cu wire is bonded onto the Ag fired cap by means of an ultrasonic wave. There is provided a semiconductor device capable of improving a power cycle capability, and a fabrication method of such a semiconductor device.

A component package and a method of forming are provided. A first component package may include a first semiconductor device having a pair of interposers attached thereto on opposing sides of the first semiconductor device. Each interposer may include conductive traces formed therein to provide electrical coupling to conductive features formed on the surfaces of the respective interposers. A plurality of through vias may provide for electrically connecting the interposers to one another. A first interposer may provide for electrical connections to a printed circuit board or subsequent semiconductor device. A second interposer may provide for electrical connections to a second semiconductor device and a second component package. The first and second component packages may be combined to form a Package-on-Package (“PoP”) structure.

A component package and a method of forming are provided. A first component package may include a first semiconductor device having a pair of interposers attached thereto on opposing sides of the first semiconductor device. Each interposer may include conductive traces formed therein to provide electrical coupling to conductive features formed on the surfaces of the respective interposers. A plurality of through vias may provide for electrically connecting the interposers to one another. A first interposer may provide for electrical connections to a printed circuit board or subsequent semiconductor device. A second interposer may provide for electrical connections to a second semiconductor device and a second component package. The first and second component packages may be combined to form a Package-on-Package (“PoP”) structure.