Disclosed is a semiconductor package comprising a first chip stack including on a substrate a plurality of first semiconductor chips in an offset stack structure and stacked to expose a connection region at a top surface of each of the first semiconductor chips, a second semiconductor chip on the substrate and horizontally spaced apart from the first chip stack, a spacer on the second semiconductor chip, and a second chip stack including third semiconductor chips in an offset stack structure on the first chip stack and the spacer. Each of the first semiconductor chips includes a first chip pad on the connection region and a first wire that extends between the first chip pad and the substrate. The first wire of an uppermost one of the first semiconductor chips is horizontally spaced apart from a lowermost one of the third semiconductor chips.

Provided is a semiconductor package having improved signal integrity (SI) and a chip stack structure of a plurality of semiconductor chips. The semiconductor package includes a package substrate, a chip stack structure on the package substrate and including at least two semiconductor chips, and an external connection terminal on a lower surface of the package substrate. A first semiconductor chip arranged uppermost in the chip stack structure is connected to a first bonding pad of the package substrate through a first wire. A second semiconductor chip arranged under the first semiconductor chip in the chip stack structure is connected to a second bonding pad of the package substrate through a second wire. When the first bonding pad is farther from the external connection terminal than the second bonding pad, the external connection terminal is connected to the first bonding pad through a wiring line of the package substrate.

A method for manufacturing a light emitting device includes: preparing a first substrate having an upper surface comprising an element placement region; placing a light emitting element in the element placement region; disposing an uncured, sheet-like light-transmissive member on the light emitting element and bringing an outer edge of a lower surface of the light-transmissive member into contact with an outer upper surface of the element placement region of the first substrate by pressing the light-transmissive member; and disposing a first protrusion portion along an outer edge of an upper surface of the light-transmissive member so that the first protrusion portion extends over the upper surface of the first substrate and the upper surface of the light-transmissive member.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first redistribution layer (RDL), having a first surface with first conductive contacts having a first pitch between 170 microns and 400 microns, an opposing second surface, and first conductive pathways between the first and second surfaces; a first die and a conductive pillar in a first layer on the first RDL; a second RDL on the first layer, the second RDL having a first surface, an opposing second surface with second conductive contacts having a second pitch between 18 microns and 150 microns, and second conductive pathways between the first and second surfaces; and a second die, in a second layer on the second RDL, electrically coupled to the first conductive contacts via the first conductive pathways, the conductive pillar, the second conductive pathways, and the second conductive contacts.

A semiconductor chip package is provided with improved connections between different components within the package. The semiconductor chip package may comprise a semiconductor chip disposed on a substrate. The semiconductor chip may have a first surface and a second surface. The first surface of the semiconductor chip may be connected to the substrate. The semiconductor chip package may comprise a leadframe that includes a first lead and a second lead. The first lead of the leadframe may be directly attached to the second surface of the semiconductor chip. The second lead of the leadframe may be directly attached to the substrate.

In one example, an electronic device structure includes a substrate having a conductive structure adjacent to a surface. The conductive structure can include a plurality of conductive pads. First and second electronic devices are disposed adjacent to the top surface. The first electronic device is interposed between a first conductive pad and a second conductive pad, and the second electronic device is interposed between the second conductive pad and a third conductive pad. A continuous wire structure including a first bond structure is connected to the first conductive pad, a second bond structure is connected to the second conductive pad, a third bond structure is connected to the third conductive pad, a first wire portion is interconnected between the first bond structure and the second bond structure and disposed to overlie the first electronic device, and a second wire portion is interconnected between the second bond structure and the third bond structure and disposed to overlie the second electronic device. Other examples and related methods are also disclosed herein.

Apparatus and methods are provided for providing provide high-speed interconnect using bond wires. According to various aspects of the subject innovation, the provided techniques may provide a ground shape to shield a high-speed signal wire from the substrate in a semiconductor assembly. In an exemplary embodiment, there is provided an assembly that may comprise a substrate, a semiconductor die attached to the substrate, a signal bond wire connecting a bond pad on the semiconductor die and a bond finger on the substrate, and a ground shape on the substrate to shield the signal wire from the substrate.

A semiconductor package includes a leadframe having a die pad and a plurality of pins disposed around the die pad, a metal interposer attached to a top surface of the die pad, and a semiconductor die attached to a top surface of the metal interposer. A plurality of bond wires with same function is bonded to the metal interposer. The die pad, the metal interposer and the semiconductor die are stacked in layers so as to form a pyramidal stack structure.

In one example, an electronic device structure includes a substrate having a conductive structure adjacent to a surface. The conductive structure can include a plurality of conductive traces. First and second electronic devices are disposed adjacent to the top surface. The first electronic device is interposed between a first conductive trace and a second conductive trace, and the second electronic device is interposed between the second conductive trace and a third conductive trace. A continuous wire structure including a first bond structure is connected to the first conductive trace, a second bond structure is connected to the second conductive trace, a third bond structure is connected to the third conductive trace, a first wire portion is interconnected between the first bond structure and the second bond structure and disposed to overlie the first electronic device, and a second wire portion is interconnected between the second bond structure and the third bond structure and disposed to overlie the second electronic device. Other examples and related methods are also disclosed herein.

A semiconductor module includes a substrate on which first, second, and third circuit boards that are electrically isolated from each other are formed; a semiconductor element arranged on the first circuit board; a connecting member that bridges an upper surface electrode of the semiconductor element and the second circuit board so as to electrically connect the upper surface electrode to the second circuit board; a wire that electrically connects the third circuit board to a first electrode that is located outside of where the first, second and third circuit boards are located in a plan view; and a sealing resin that covers and seals the substrate, the semiconductor element, the connecting member, and the wire, wherein the wire is wired from the third circuit board to the first electrode so as to cross the semiconductor element at a vertical position lower than an upper surface of the connecting member.