A half bridge power module (1) comprising a substrate (2) comprising an inner load track (11), two intermediate load tracks (12, 14) and two outer load tracks (10,13), wherein an external terminal is mounted on one of the intermediate load tracks (12, 14), an external terminal (3, 4) is mounted on one of the outer load tracks (10, 13) and an external terminal (5) is mounted on the inner load track (11); wherein semiconductor switches (101, 12, 105, 106) are mounted on the outer load tracks (10, 13) and are electrically connected to the intermediate load track (12); and semiconductor switches (103, 104, 107, 108) are mounted on the intermediate load tracks (12, 14) and are electrically connected to the inner load track (11).

An integrated circuit package includes a transmission line structure, wire bonds, a first post and a second post. The transmission line structure runs from a printed circuit board (PCB) to an integrated circuit (IC) and includes a center transmission line between two ground lines and sealed from exposure to air. The wire bonds connect the transmission line structure to pads on the integrated circuit from where the center transmission line exits the integrated circuit package. The wire bonds are selected to have an impedance matched to impedance of the integrated circuit. The first post supports the center transmission line where the center transmission line enters the integrated circuit package from the printed circuit board. The second post supports the center transmission line where the center transmission line exits the integrated circuit package to connect to the wire bonds.

Memory devices and associated methods and systems are disclosed herein. A representative memory device includes a substrate and a memory controller electrically coupled to the substrate. The memory controller can include a first in/out (I/O) channel and a second I/O channel. The memory device can further include a plurality of first memories and second memories coupled to the substrate and arranged in a stack in which the first memories are interleaved between the second memories. The memory device can further include (i) a plurality of first wire bonds electrically coupling the first memories to the first I/O channel of the memory controller and (ii) a plurality of second wire bonds electrically coupling the second memories to the second I/O channel.

Disclosed is a package for a semiconductor device including a semiconductor die. The package includes a base member, a side wall, first and second conductive films, and first and second conductive leads. The base member has a conductive main surface including a region that mounts the semiconductor die. The side wall surrounds the region and is made of a dielectric. The side wall includes first and second portions. The first and second conductive films are provided on the first and second portions, respectively and are electrically connected to the semiconductor die. The first and second conductive leads are conductively bonded to the first and second conductive films, respectively. At least one of the first and second portions includes a recess in its back surface facing the base member, and the recess defines a gap between the at least one of the first and second portions below the corresponding conductive film and the base member.

In a semiconductor device, a first structure including a first uneven unit and a second structure covering the first structure and including a second uneven unit are formed in a bonding region defined in a semiconductor substrate. Metal wiring is joined to the second uneven unit in the second structure. A depth of a recess in the second uneven unit is shallower than a depth of a recess in the first uneven unit. An insulating member defining the bonding region is formed so as to reach the semiconductor substrate.

A display apparatus including a panel substrate, and a light emitting source disposed on the panel substrate, in which the light emitting source includes a substrate, an electrode disposed on the substrate, a light emitting structure disposed on the electrode and having an n-type semiconductor layer, a p-type semiconductor layer, an n-type electrode, and a p-type electrode, a transparent electrode disposed on the light emitting structure, and an adhesive layer disposed on the light emitting structure, the n-type electrode is electrically connected to the electrode, the p-type electrode is electrically connected to the transparent electrode, and the adhesive layer is disposed between the p-type electrode and the transparent electrode.

Provided are a power device, a sensor which measures a physical state of the power device to transmit a signal according to the physical state, a main electrode terminal through which a main current of the power device flows, a sensor signal terminal which is connected to the sensor to receive a signal from the sensor, a driving terminal which receives driving power for driving the power device, and an open bottomed case which houses the power device, the sensor, the main electrode terminal, the sensor signal terminal and the driving terminal, the sensor signal terminal and the driving terminal each having a first terminal and a second terminal which are provided away from an inner side wall surface of the case, the first and second terminals electrically conducting to each other to form a double structure.

A packaging structure is provided, including a substrate, a first chip, a second chip, and a conductive unit. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip by the conductive unit.

A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture.

A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture.