A semiconductor structure is provided. The semiconductor structure includes a first semiconductor device. The semiconductor structure includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first oxide layer formed below the a first substrate, a first bonding layer formed below the first oxide layer, and a first bonding via formed through the first bonding layer and the first oxide layer. The second semiconductor device includes a second oxide layer formed over a second substrate, a second bonding layer formed over the second oxide layer, and a second bonding via formed through the second bonding layer and the second oxide layer. The semiconductor structure also includes a bonding structure between the first substrate and the second substrate, and the bonding structure includes the first bonding via bonded to the second bonding via.

The present disclosure provides a method for manufacturing a semiconductor package. The method includes disposing a first semiconductor substrate on a temporary carrier and dicing the first semiconductor substrate to form a plurality of dies. Each of the plurality of dies has an active surface and a backside surface opposite to the active surface. The backside surface is in contact with the temporary carrier and the active surface faces downward. The method also includes transferring one of the plurality of dies from the temporary carrier to a temporary holder. The temporary holder only contacts a periphery portion of the active surface of the one of the plurality of dies.

According to one embodiment, in a substrate bonding apparatus a first chucking stage includes a first stage base, a plurality of first cylindrical members, and a plurality of first drive mechanisms. The first stage base includes a first main face facing a second chucking stage. The plurality of first cylindrical members are disposed on the first main face. The plurality of first cylindrical members are arrayed in planar directions. The plurality of first cylindrical members protrudes from the first main face in a direction toward the second chucking stage to chuck the first substrate. The plurality of first drive mechanisms are configured to drive the plurality of first cylindrical members independently of each other. The substrate bonding apparatus further comprises a first pressure control mechanism configured to control pressure states of spaces in the plurality of first cylindrical members independently of each other.

According to one embodiment, there is provided a substrate bonding apparatus including a first chucking stage, a second chucking stage, and an alignment unit. The first chucking stage is configured to chuck a first substrate. The second chucking stage is disposed facing the first chucking stage. The second chucking stage is configured to chuck a second substrate. The alignment unit is configured to be inserted between the first chucking stage and the second chucking stage. The alignment unit includes a base body, a first detection element, and a second detection element. The base body includes a first main face and a second main face opposite to the first main face. The first detection element is disposed on the first main face. The second detection element is disposed on the second main face.

A method includes determining a first offset between a first alignment mark on a first side of a first wafer and a second alignment mark on a second side of the first wafer; aligning the first alignment mark of the first wafer to a third alignment mark on a first side of a second wafer, which includes detecting a location of the second alignment mark of the first wafer; determining a location of the first alignment mark of the first wafer based on the first offset and the location of the second alignment mark of the first wafer; and, based on the determined location of the first alignment mark, repositioning the first wafer to align the first alignment mark to the third alignment mark; and bonding the first side of the first wafer to the first side of the second wafer to form a bonded structure.

Alignment of a first wafer bonded to a second wafer can be determined using electrical wafer alignment methods. A wafer stack can be formed by overlaying a second wafer over a first wafer such that second metal bonding pads of the second wafer contact first metal bonding pads of the first wafer. A leakage current or a capacitance measurement step is performed between first alignment diagnostic structures in the first wafer and second alignment diagnostic structures in the second wafer for multiple mating pairs of first semiconductor dies in the first wafer and second semiconductor dies in the second wafer to determine the alignment.

A method for placing a semiconductor onto a substrate is provided. The method includes the following steps: transferring, using a placement tool, the semiconductor along a path over onto the substrate; lowering, using the placement tool, the semiconductor to a predetermined height above the substrate; titling, using the placement tool, the semiconductor, to a predetermined angle; determining, using the placement tool, a first contact point of the semiconductor to the substrate at the predetermined angle; determining, using the placement tool, the first contact point is shift-off from an alignment position on the semiconductor with respect to the substrate; adjusting, using the placement tool, the first contact point to correct the shift-off; and lowering, using the placement tool, the semiconductor to make a first contact with the substrate at the corrected first contact point.

A method includes determining a first offset between a first alignment mark on a first side of a first wafer and a second alignment mark on a second side of the first wafer; aligning the first alignment mark of the first wafer to a third alignment mark on a first side of a second wafer, which includes detecting a location of the second alignment mark of the first wafer; determining a location of the first alignment mark of the first wafer based on the first offset and the location of the second alignment mark of the first wafer; and, based on the determined location of the first alignment mark, repositioning the first wafer to align the first alignment mark to the third alignment mark; and bonding the first side of the first wafer to the first side of the second wafer to form a bonded structure.

A method includes determining a first offset between a first alignment mark on a first side of a first wafer and a second alignment mark on a second side of the first wafer; aligning the first alignment mark of the first wafer to a third alignment mark on a first side of a second wafer, which includes detecting a location of the second alignment mark of the first wafer; determining a location of the first alignment mark of the first wafer based on the first offset and the location of the second alignment mark of the first wafer; and, based on the determined location of the first alignment mark, repositioning the first wafer to align the first alignment mark to the third alignment mark; and bonding the first side of the first wafer to the first side of the second wafer to form a bonded structure.

Alignment of a first wafer bonded to a second wafer can be determined using electrical wafer alignment methods. A wafer stack can be formed by overlaying a second wafer over a first wafer such that second metal bonding pads of the second wafer contact first metal bonding pads of the first wafer. A leakage current or a capacitance measurement step is performed between first alignment diagnostic structures in the first wafer and second alignment diagnostic structures in the second wafer for multiple mating pairs of first semiconductor dies in the first wafer and second semiconductor dies in the second wafer to determine the alignment.