H01L2224/85075

SEMICONDUCTOR DIE WITH STEPPED SIDE SURFACE
20230017286 · 2023-01-19 ·

A semiconductor device includes a substrate and a semiconductor die including an active surface with bond pads, an opposite inactive surface, and stepped side surfaces extending between the active surface and the inactive surface. The stepped side surfaces include a first planar surface extending from the inactive surface towards the active surface, a second planar surface extending from the active surface towards the inactive surface, and a side surface offset between the first planar surface and the second planar surface. The semiconductor device further includes an adhesive layer covering at least a portion of a surface area of the second surface and attaching the semiconductor die to the substrate.

SEMICONDUCTOR DIE WITH STEPPED SIDE SURFACE
20230017286 · 2023-01-19 ·

A semiconductor device includes a substrate and a semiconductor die including an active surface with bond pads, an opposite inactive surface, and stepped side surfaces extending between the active surface and the inactive surface. The stepped side surfaces include a first planar surface extending from the inactive surface towards the active surface, a second planar surface extending from the active surface towards the inactive surface, and a side surface offset between the first planar surface and the second planar surface. The semiconductor device further includes an adhesive layer covering at least a portion of a surface area of the second surface and attaching the semiconductor die to the substrate.

WIRE GUIDE MODULE, AND ULTRASONIC WIRE BONDER THEREWITH

A wire guide module for an ultrasonic wire bonder, comprising a body made of a thermally stable metallic and/or ceramic material, wherein an elongated wire feed-through channel having a wire inlet opening and having a wire outlet opening is provided on the body, and comprising a guide tube provided in the wire feed-through channel. In addition, the invention relates to a thermosonic wire bonder having a wire guide module.

COPPER BONDING WIRE

There is provided a copper bonding wire that exhibits a favorable bondability even when a scrub at the time of bonding is reduced. The copper bonding wire is characterized in that when a sum of percentages of Cu, Cu.sub.2O, CuO and Cu(OH).sub.2 on a surface of the wire as measured by X-ray Photoelectron Spectroscopy (XPS) is defined as 100%, Cu[II]/Cu[I] which is a ratio of a total percentage of CuO and Cu(OH).sub.2 (Cu[II]) corresponding to bivalent Cu to a percentage of Cu.sub.2O (Cu[I]) corresponding to monovalent Cu falls within a range from 0.8 to 12.

COPPER BONDING WIRE

There is provided a copper bonding wire that exhibits a favorable bondability even when a scrub at the time of bonding is reduced. The copper bonding wire is characterized in that when a sum of percentages of Cu, Cu.sub.2O, CuO and Cu(OH).sub.2 on a surface of the wire as measured by X-ray Photoelectron Spectroscopy (XPS) is defined as 100%, Cu[II]/Cu[I] which is a ratio of a total percentage of CuO and Cu(OH).sub.2 (Cu[II]) corresponding to bivalent Cu to a percentage of Cu.sub.2O (Cu[I]) corresponding to monovalent Cu falls within a range from 0.8 to 12.

BONDING WIRE FOR SEMICONDUCTOR DEVICE
20170365576 · 2017-12-21 ·

The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 μm in thickness.

BONDING WIRE FOR SEMICONDUCTOR DEVICE
20170365576 · 2017-12-21 ·

The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 μm in thickness.

STRUCTURE AND METHOD FOR STABILIZING LEADS IN WIRE-BONDED SEMICONDUCTOR DEVICES

A semiconductor device having a leadframe including a pad (101) surrounded by elongated leads (110) spaced from the pad by a gap (113) and extending to a frame, the pad and the leads having a first thickness (115) and a first and an opposite and parallel second surface; the leads having a first portion (112) of first thickness near the gap and a second portion (111) of first thickness near the frame, and a zone (114) of reduced second thickness (116) between the first and second portions; the second surface (112a) of the first lead portions is coplanar with the second surface (111a) of the second portions. A semiconductor chip (220) with a terminal is attached the pad. A metallic wire connection (230) from the terminal to an adjacent lead includes a stitch bond (232) attached to the first surface of the lead.

STRUCTURE AND METHOD FOR STABILIZING LEADS IN WIRE-BONDED SEMICONDUCTOR DEVICES

A semiconductor device having a leadframe including a pad (101) surrounded by elongated leads (110) spaced from the pad by a gap (113) and extending to a frame, the pad and the leads having a first thickness (115) and a first and an opposite and parallel second surface; the leads having a first portion (112) of first thickness near the gap and a second portion (111) of first thickness near the frame, and a zone (114) of reduced second thickness (116) between the first and second portions; the second surface (112a) of the first lead portions is coplanar with the second surface (111a) of the second portions. A semiconductor chip (220) with a terminal is attached the pad. A metallic wire connection (230) from the terminal to an adjacent lead includes a stitch bond (232) attached to the first surface of the lead.

BONDING WIRE FOR SEMICONDUCTOR DEVICE

There is provided a Cu bonding wire having a Pd coating layer on a surface thereof, that improves bonding reliability of a ball bonded part in a high-temperature and high-humidity environment and is suitable for on-vehicle devices.

The bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface of the Cu alloy core material, and the bonding wire contains In of 0.011 to 1.2% by mass and has the Pd coating layer of a thickness of 0.015 to 0.150 μm. With this configuration, it is able to increase the bonding longevity of a ball bonded part in a high-temperature and high-humidity environment, and thus to improve the bonding reliability. When the Cu alloy core material contains one or more elements of Pt, Pd, Rh and Ni in an amount, for each element, of 0.05 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 175° C. or more. When an Au skin layer is further formed on a surface of the Pd coating layer, wedge bondability improves.