A metal base plate is rectangular in plan view, has a joining region set on a front surface, and has a center line, which is parallel to a pair of short sides that face each other, set in a middle interposed between the pair of short sides. A ceramic circuit board includes a ceramic board that is rectangular in plan view, a circuit pattern that is formed on a front surface of the ceramic board and has a semiconductor chip joined thereto, and a metal plate that is formed on a rear surface of the ceramic board and is joined to the joining region by solder. Here, the solder contains voids and is provided with a stress relieving region at one edge portion that is away from the center line. A density of voids included in the stress relieving region is higher than other regions of the solder.

Articles, devices, and methods including anisotropic van der Waals thermal conductors are described.

Some implementations of the disclosure are directed to a thermal interface material. In some implementations, a method comprises: applying a solder paste between a surface of a heat generating device and a surface of a heat transferring device to form an assembly; and reflow soldering the assembly to form a solder composite, wherein the solder composite provides a thermal interface between the heat generating device and the heat transferring device, wherein the solder paste comprises: a solder powder; particles having a higher melting temperature than a soldering temperature of the solder paste, wherein the solder paste has a volume ratio of solder powder to high melting temperature particles between 5:1 and 1:1.5; and flux.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface, wherein the first surface of the die is coupled to the surface of the package substrate; and a cooling apparatus that may include a conductive base having a first surface and an opposing second surface, wherein the first surface of the conductive base is in thermal contact with the second surface of the die, and a plurality of conductive structures on the second surface of the conductive base, wherein an individual conductive structure of the plurality of conductive structures has a width between 10 microns and 100 microns.

Systems for cooling semiconductor devices that can comprise a heatsink and a cleaning element for the heatsink. The heatsink can have fins spaced apart from each other by channels. The cleaning element can have a base and one or more arms extending from the base. The cleaning element can be positioned with respect to the heatsink such that each arm is aligned with a corresponding channel between the fins, and the arms are moveable between a flow configuration in which the arms are in the channels and a cleaning configuration in which the arms are outside of the channels.

Provided is anisotropic graphite for producing an anisotropic graphite composite having excellent thermal conduction property and excellent long-term reliability as a heat dissipating member. Given an X axis, a Y axis orthogonal to the X axis, and a Z axis perpendicular to a plane defined by the X axis and the Y axis, and a crystal orientation plane of the anisotropic graphite is parallel to an X-Z plane, and a specific number of holes each having a specific size are formed in at least one surface out of surfaces of the anisotropic graphite which are parallel to an X-Y plane.

An integrated circuit package that includes a liquid phase thermal interface material (TIM) is described. The package may include any number of die. The liquid phase TIM can be sealed in a chamber between a die and an integrated heat spreader and bounded on the sides by a perimeter layer. The liquid phase TIM can be fixed in place or circulated, depending on application. A thermal conductivity of the liquid phase TIM can be at least 15 Watts/meter-Kelvin, according to some embodiments. A liquid phase TIM eliminates failure mechanisms present in solid phase TIMs, such as cracking due to warpage and uncontained flow out of the module.

A chip is mounted on a surface of the substrate, and the thermally conductive cover is disposed on a side that is of the chip and that is away from the substrate. There is a filling area on a surface that is of the thermally conductive cover and that faces the substrate, and the filling area is opposite to the chip. There is an accommodation cavity whose opening faces the substrate in the filling area. A thermal interface material layer is filled between the chip and a bottom surface of the accommodation cavity. Between an opening edge of the accommodation cavity and the substrate, there is a first gap connected to the accommodation cavity. The filling material encircles a side surface of the thermal interface material layer, so that the filling material separates the side surface of the thermal interface material layer from air.

A ceramic circuit board includes a ceramic base material, a metal layer (first metal layer), and a marker portion. The marker portion is formed on the surface of the first metal layer. The surface of the metal layer (first metal layer) may be plated. When the surface of the metal layer (first metal layer) is plated, the marker portion may be formed on the plating.

Semiconductor device assemblies are provided with a package substrate including one or more layers of thermally conductive material configured to conduct heat generated by one or more of semiconductor dies of the assemblies laterally outward towards an outer edge of the assembly. The layer of thermally conductive material can comprise one or more allotropes of carbon, such as diamond, graphene, graphite, carbon nanotubes, or a combination thereof. The layer of thermally conductive material can be provided via deposition (e.g., sputtering, PVD, CVD, or ALD), via adhering a film comprising the layer of thermally conductive material to an outer surface of the package substrate, or via embedding a film comprising the layer of thermally conductive material to within the package substrate.