A metal base plate is rectangular in plan view, has a joining region set on a front surface, and has a center line, which is parallel to a pair of short sides that face each other, set in a middle interposed between the pair of short sides. A ceramic circuit board includes a ceramic board that is rectangular in plan view, a circuit pattern that is formed on a front surface of the ceramic board and has a semiconductor chip joined thereto, and a metal plate that is formed on a rear surface of the ceramic board and is joined to the joining region by solder. Here, the solder contains voids and is provided with a stress relieving region at one edge portion that is away from the center line. A density of voids included in the stress relieving region is higher than other regions of the solder.

A circuit module includes a substrate with a patterned metal surface. The patterned metal surface includes a conductive terminal pad, a first conductive pad, and a second conductive pad that is non-adjacent to the conductive terminal pad. A first circuit portion is assembled on the first conductive pad and a second circuit portion is assembled on the second conductive pad. A conductive bridge electrically couples the conductive terminal pad and the second conductive pad. The conductive bridge includes an elevated span extending above and across the first conductive pad.

A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.

A terminal member connected to a connection target portion includes: a bent portion bent toward the connection target portion; and a tip connection portion provided at a tip part of the bent portion, in which the tip connection portion is connected to the connection target portion via a conductive bonding material.

A semiconductor sub-assembly and a semiconductor power module capable of having the reduced thickness of a chip and reduced thermal resistance are provided. The semiconductor sub-assembly includes a single or a plurality of semiconductor chips having a first electrode that is formed on the lower surface thereof, a second electrode that is formed on the upper surface thereof, and a plurality of chip-side signal electrode pads that are formed at one end of the upper surface thereof. The semiconductor chip is embedded in the embedded structure and a plurality of extension signal electrode pads are connected to each of the chip-side signal electrode pads. The extension signal electrode pad is formed on the embedded substrate in a size greater than the chip-side signal electrode pad when viewed on the plane.

A semiconductor device includes a metal base plate, a case component, and a metal component. The metal component is fixed to the case component. A partial region of the metal component is exposed from the case component. The partial region is bonded to the base plate in a bonding portion. In the bonding portion, a surface of the partial region and a surface of the base plate are in direct contact with each other and integrated.

Provided is a small-sized inexpensive semiconductor module in which increase of ON resistance and increase of turn-off surge voltage at low temperature are suppressed. The semiconductor module includes: a semiconductor switching element; and a stress application portion provided on one or each of a first surface and a second surface on an opposite side to the first surface of the semiconductor switching element, having a linear expansion coefficient larger than that of a main material of the semiconductor switching element, and having a larger thickness than the semiconductor switching element. The stress application portion generates compressive or tensile stress in the semiconductor switching element through thermal shrinkage or expansion of the stress application portion due to change in temperature. A threshold voltage at which the semiconductor switching element is turned on, decreases in association with increase of a magnitude of the compressive or tensile stress in the semiconductor switching element.

A semiconductor device manufacturing method includes preparing a semiconductor chip and a conductive plate having a front surface that includes a disposition area on which the semiconductor chip is to be disposed, forming a supporting portion in a periphery of the disposition area of the conductive plate such that the supporting portion protrudes from a bottom of the disposition area in an upward direction orthogonal to the front surface of the conductive plate, bonding the semiconductor chip to the disposition area via bonding material applied to the disposition area, coating the front surface of the conductive plate, including the semiconductor chip and the supporting portion, with a coating layer, and after the coating, sealing the front surface of the conductive plate, including the semiconductor chip and the supporting portion, with sealing material.

Embodiments herein relate to systems, apparatuses, or processes for forming a decoupling capacitor within a multilayer die using hybrid bonding. Dummy bond pads may be used to form plates for the capacitor and a high-k dielectric material may be deposited between the plates prior to hybrid bonding. Other embodiments may be described and/or claimed.

A power semiconductor module includes a metal bottom plate, an insulating heat dissipation material layer, a chip, a binding plate, silica gel, and an outer housing, where the binding plate includes a copper plate and a copper strap. The copper plate is connected to the copper strap through welding, and the binding plate is configured to connect circuits of various components. The metal bottom plate is connected to the insulating heat dissipation material layer through tin soldering, the chip is connected to the insulating heat dissipation material layer through tin soldering, the chip is connected to the copper strap, and the copper strap is connected to the insulating heat dissipation material layer. The module can resolve the prior-art problem of mechanical stress generated on the chip in the case of a temperature change when a relatively thick copper frame is applied to the packaging of the power semiconductor module.