An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.

A transient electronic device utilizes a glass-based interposer that is treated using ion-exchange processing to increase its fragility, and includes a trigger device operably mounted on a surface thereof. An integrated circuit (IC) die is then bonded to the interposer, and the interposer is mounted to a package structure where it serves, under normal operating conditions, to operably connect the IC die to the package I/O pins/balls. During a transient event (e.g., when unauthorized tampering is detected), a trigger signal is transmitted to the trigger device, causing the trigger device to generate an initial fracture force that is applied onto the glass-based interposer substrate. The interposer is configured such that the initial fracture force propagates through the glass-based interposer substrate with sufficient energy to both entirely powderize the interposer, and to transfer to the IC die, whereby the IC die also powderizes (i.e., visually disappears).

A device and a method for implementing a physically unclonable function is disclosed. In one aspect, the device includes at least one electronic structure including a dielectric. A conductive path is formed at a random position through the dielectric due to an electrical breakdown of the dielectric, or the electronic structure is adapted for generating an electrical breakdown of the dielectric such that the conductive path is formed through the dielectric at a random position. The at least one electronic structure is adapted for determining a distinct value of a set comprising at least two predetermined values. The distinct value is determined by the position of the conductive path through the dielectric.

Systems and methods for obfuscating a circuit design are described. One of the methods includes receiving the circuit design from a user computing device. The circuit design includes a plurality of circuit components. The method further includes obfuscating each of the circuit components by transforming layout features associated with the circuit design into a generic layout feature representation. The generic layout feature representation excludes scaled representations of the layout features. The method also includes generating a visual representation of the obfuscated designs. Each of the obfuscated designs has an input port and an output port. The method further includes enabling placement of the obfuscated designs and routing between the input ports and the output ports of the obfuscated designs. The method includes generating an obfuscated integrated circuit design having a master input port, a master output port, the obfuscated designs, and the routing between the obfuscated designs.

An optically occlusive protective element for bonded structures, embodiments of which disclosed herein relate to directly bonded structures along a bond interface. Specifically, two elements, a semiconductor element and an occlusive element, may be directly bonded to one another without an intervening adhesive along a bonding interface. The semiconductor element includes active circuitry which, after bonding, is protected by the occlusive element. The occlusive element includes several optically occlusive layers which are arranged to inhibit an optical interrogation of the active circuitry. Such layers may further include occlusive strips which may or may not overlap with other occlusive strips from other occlusive layers when the occlusive layers are stacked vertically.

An electronic chip includes at least an electronic circuit disposed on a front face of a substrate; and an embrittlement structure comprising at least blind holes, each extending through a rear face of the substrate and a portion of the thickness of the substrate and each having a section, in a plane parallel to the rear face of the substrate, of surface area S and having a closed outer contour, the shape of which includes at least one radius of curvature R, such that S>π.Math.R.sup.2.

Systems and methods for overmolding a card are provided. A chip fraud prevention system include a device including a chip and a substrate. The chip may be at least partially encompassed in a chip pocket, and the substrate may be at least partially encompassed by the overmold.

A method of making a semiconductor device includes electrically connecting a component to a first side of a first fuse, wherein the first fuse is a first distance from the component. The method further includes electrically connecting the component to a first side of a second fuse, wherein the second fuse is a second distance from the component, and the second distance is different than the first distance. The method further includes electrically connecting a second side of the second fuse to a dummy vertical interconnect segment.

Disclosed is an organic light emitting display device including a dam structure disposed in a non-display area of a substrate and an alignment mark disposed outside the dam structure. The alignment mark is not covered by, and does not overlap with, the dam structure, because the alignment mark is disposed outside the dame structure. Thus, a scribing process may be performed smoothly.

An integrated circuit (IC) is provided that includes a plurality of physical unclonable function (PUF) structures located in a PUF area. Each PUF structure of the plurality of PUF structures includes at least a PUF top electrically conductive structure containing random sidewall voids and random line openings which can provide an encrypted security code to the IC. The IC further includes a plurality of memory structures located in a memory area that is located laterally adjacent to the PUF area. Each memory structure of the plurality of memory structures includes a memory element sandwiched between a bottom electrically conductive structure and a top electrically conductive structure. The top electrically conductive structures are devoid of sidewall voids and line openings.