A semiconductor device comprising a wiring member with which a semiconductor chip is electrically connected including: a first wiring layer having a plurality of first conductive patterns; a second wiring layer arranged next to the first wiring layer in a thickness direction of the wiring member, and having a second conductive pattern; and a third wiring layer arranged next to the second wiring layer in the thickness direction of the wiring member, and having a third conductive pattern. Here, in plan view, a first opening portion of each of two, which are arranged next to each other, of a plurality of first opening portions each penetrating through the second conductive pattern is overlapped with a pair of differential signal wirings contained in plurality of first conductive patterns, and is overlapped with two or more of a plurality of second opening portions each penetrating through the third conductive pattern.

An electronic device is provided. The electronic device includes: a substrate, a first light-emitting element, and a second light-emitting element. The first light-emitting element is disposed on the substrate and configured to emit a first color light under a first current density when the substrate provides a first current to the first light-emitting element. The second light-emitting element is disposed on the substrate and configured to emit a second color light under a second current density when the substrate provides a second current to the second light-emitting element. The first current is equal to the second current, and the first current density is different from the second current density.

Contact bumps between a contact pad and a substrate can include a rough surface that can mate with the material of the substrate of which may be flexible. The rough surface can enhance the bonding strength of the contacts, for example, against shear and tension forces, especially for flexible systems such as smart label and may be formed via roller or other methods.

A semiconductor device comprising a wiring member with which a semiconductor chip is electrically connected including: a first wiring layer having a plurality of first conductive patterns; a second wiring layer arranged next to the first wiring layer in a thickness direction of the wiring member, and having a second conductive pattern; and a third wiring layer arranged next to the second wiring layer in the thickness direction of the wiring member, and having a third conductive pattern. Here, in plan view, a first opening portion of each of two, which are arranged next to each other, of a plurality of first opening portions each penetrating through the second conductive pattern is overlapped with a pair of differential signal wirings contained in plurality of first conductive patterns, and is overlapped with two or more of a plurality of second opening portions each penetrating through the third conductive pattern.

A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.

An electronic device and a method for producing an electronic device are disclosed. In an embodiment the electronic device includes a first component and a second component and a sinter layer connecting the first component to the second component, the sinter layer comprising a first metal, wherein at least one of the components comprises at least one contact layer which is arranged in direct contact with the sinter layer, which comprises a second metal different from the first metal and which is free of gold.

Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device is formed by connecting a top package and a bottom package together using a plurality of PoP connectors on the bottom package connected to corresponding connectors of the top package. The PoP device further comprises a plurality of dummy connectors contained in the bottom package and not connected to any corresponding connector in the top package.

An electronic device is provided. The electronic device includes a substrate and another substrate disposed opposite to the substrate. The electronic device includes a first light-emitting element disposed on the substrate and configured to emit blue light under a first current density when the substrate provides a first current to the first light-emitting element. The electronic device includes a second light-emitting element disposed on the substrate and configured to emit green light or red light under a second current density when the substrate provides a second current to the second light-emitting element. The electronic device includes a protective layer disposed between the substrate and the another substrate and covering the first light-emitting element and the second light-emitting element. The electronic device includes an adhesive layer disposed between the protective layer and the another substrate.

Devices and methods that can facilitate hybrid under-bump metallization components are provided. According to an embodiment, a device can comprise an under-bump metallization component that can comprise a superconducting interconnect component and a solder wetting component. The device can further comprise a solder bump that can be coupled to the superconducting interconnect component and the solder wetting component. In some embodiments, the superconducting interconnect component can comprise a hermetically sealed superconducting interconnect component.

An integrated circuit component including a semiconductor die, a plurality of conductive vias and a protection layer is provided. The semiconductor die includes an active surface and a plurality of conductive pads disposed on the active surface. The conductive vias are respectively disposed on and in contact with the conductive pads, wherein each conductive via of a first group of the conductive vias has a first maximum size, each conductive via of a second group of the conductive vias has a second maximum size, and the first maximum size is less than the second maximum size in a vertical projection on the active surface. The protection layer covers the active surface and is at least in contact with sidewalls of the conductive vias.