Semiconductor dice are arranged on a substrate such as a leadframe. Each semiconductor die is provided with electrically-conductive protrusions (such as electroplated pillars or bumps) protruding from the semiconductor die opposite the substrate. Laser direct structuring material is molded onto the substrate to cover the semiconductor dice arranged thereon, with the molding operation leaving a distal end of the electrically-conductive protrusion to be optically detectable at the surface of the laser direct structuring material. Laser beam processing the laser direct structuring material is then performed with laser beam energy applied at positions of the surface of the laser direct structuring material which are located by using the electrically-conductive protrusions optically detectable at the surface of the laser direct structuring material as a spatial reference.

An apparatus for securing a wafer includes a chuck, at least one O-ring disposed on the chuck, a vacuum system connected to the chuck, such that the vacuum system comprises a plurality of vacuum holes through the chuck connected to one or more vacuum pumps, and a controller configured to control the height of the at least one O-ring relative to the top surface of the chuck. The controller is connected to pressure sensors capable of detecting a vacuum. The at least one O-ring may include a plurality of O-rings.

An apparatus for securing a wafer includes a chuck, at least one O-ring disposed on the chuck, a vacuum system connected to the chuck, such that the vacuum system comprises a plurality of vacuum holes through the chuck connected to one or more vacuum pumps, and a controller configured to control the height of the at least one O-ring relative to the top surface of the chuck. The controller is connected to pressure sensors capable of detecting a vacuum. The at least one O-ring may include a plurality of O-rings.

A semiconductor package includes a plurality of stack modules which are vertically stacked. Each of the stack modules includes an interposing bridge, a semiconductor dies, and redistribution lines. The stack modules are provided by rotating each of the stack modules by different rotation angles corresponding to multiples of a reference angle and by vertically stacking the rotated stack modules. The interposing bridge includes a plurality of sets of through vias, and each set of through vias includes through vias arrayed in a plurality of columns. The plurality of sets of through vias are disposed in respective ones of divided regions of the interposing bridge. If the plurality of sets of through vias are rotated by the reference angle, then the rotated through vias overlap with the plurality of sets of through vias which are originally located. The redistribution lines connect the semiconductor dies to the plurality of sets of through vias.

Panel level packaging (PLP) with high accuracy and high scalability is disclosed. The PLP employs an alignment carrier with a low coefficient of expansion which is configured with die regions having local die alignment marks. For example, local die alignment marks are provided for each die attach region. Depending on the size of the panel, it may be segmented into blocks, each with die regions with local die alignment marks. In addition, a block includes an alignment die region configured for attaching an alignment die. Linear and non-linear positional errors are reduced due to local die alignment marks and alignment dies. The use of local die alignment marks and alignment dies results in increase yields as well as scaling, thereby improving throughput and decreasing overall costs.

A method for manufacturing a semiconductor package structure and a semiconductor manufacturing apparatus are provided. The method includes: (a) providing a package body disposed on a chuck, wherein the package body includes at least one semiconductor element encapsulated in an encapsulant; and (b) sucking the package body through the chuck to create a plurality of negative pressures on a bottom surface of the package body sequentially from an inner portion to an outer portion of the package body.

A package structure including a lead frame structure, a die, an adhesive layer, and at least one three-dimensional (3D) printing conductive wire is provided. The lead frame structure includes a carrier and a lead frame. The carrier has a recess. The lead frame is disposed on the carrier. The die is disposed in the recess. The die includes at least one pad. The adhesive layer is disposed between a bottom surface of the die and the carrier and between a sidewall of the die and the carrier. The 3D printing conductive wire is disposed on the lead frame, the adhesive layer, and the pad, and is electrically connected between the lead frame and the pad.

The invention relates to a method (110) for producing an electrically conductive connection (112, 112′) on a substrate (114), comprising the following steps: a) providing a substrate (114), wherein the substrate (114) is configured for receiving an electrically conductive connection (112, 112′); b) providing a reservoir of an electrically conductive liquid alloy, wherein the reservoir has a surface at which the alloy has an insulating layer; c) providing a capillary (120) configured for taking up the electrically conductive liquid alloy; d) penetrating of a tip (122) of the capillary (120) under the surface of the reservoir and taking up of a portion of the alloy from the reservoir; and e) applying the portion of the alloy at least partly to the substrate (114) in such a manner that an electrically conductive connection (112, 112′) is formed from the alloy on the substrate (114), wherein the alloy remains on the substrate (114) by adhesion.

The invention furthermore relates to a method for producing a microelectronic device (124) and to a microelectronic device (124), in particular a transistor (130).

A method includes, receiving a layout design of at least part of an electronic module, the design specifying at least (i) an electronic device coupled to at least a substrate, and (ii) an electrical trace that is connected to the electronic device and has a designed route. A digital input, which represents at least part of an actual electronic module that was manufactured in accordance with the layout design but without at least a portion of the electrical trace, is received. An error in coupling the electronic device to the substrate, relative to the layout design, is estimated based on the digital input. An actual route that corrects the estimated error, is calculated for at least the portion of the electrical trace. At least the portion of the electrical trace is formed on the substrate of the actual electronic module, along the actual route instead of the designed route.

A method includes, receiving a layout design of at least part of an electronic module, the design specifying at least (i) an electronic device coupled to at least a substrate, and (ii) an electrical trace that is connected to the electronic device and has a designed route. A digital input, which represents at least part of an actual electronic module that was manufactured in accordance with the layout design but without at least a portion of the electrical trace, is received. An error in coupling the electronic device to the substrate, relative to the layout design, is estimated based on the digital input. An actual route that corrects the estimated error, is calculated for at least the portion of the electrical trace. At least the portion of the electrical trace is formed on the substrate of the actual electronic module, along the actual route instead of the designed route.