The present technique relates to an electrostatic protective element that enables protective performance with respect to static electricity to be improved and to an electronic device. An electrostatic protective element includes: a first impurity region of a first conductivity type which is formed on the predetermined surface side of a semiconductor substrate; a second impurity region of a second conductivity type which is formed on the predetermined surface side of the semiconductor substrate so as to form a clearance in a horizontal direction with respect to the first impurity region; a collector contact which is formed on the predetermined surface side in the first impurity region, which has a higher concentration than the first impurity region, and which is an impurity region of the first conductivity type; a base contact which is formed on the predetermined surface side in the second impurity region, which has a higher concentration than the second impurity region, and which is an impurity region of the second conductivity type; and an emitter contact which is formed on the predetermined surface side in the second impurity region at a position that is closer to the collector contact than the base contact, which has a higher concentration than the second impurity region, and which is an impurity region of the first conductivity type. The present technique can be applied to, for example, an electronic device.

The present disclosure provides an electronic device that includes a substrate. The substrate includes a well and a peripheral insulating wall laterally surrounding the well. At least one lateral bipolar transistor is formed in the well, and the at least one transistor has a base region extending under parallel collector and emitter regions. The peripheral insulating wall is widened in a first direction, parallel to the collector and emitter regions, so that the base region penetrates into the peripheral insulating wall.

High voltage clamps with transient activation and activation release control are provided herein. In certain configurations, an integrated circuit (IC) includes a clamp electrically connected between a first node and a second node and having a control input. The IC further includes a first resistor-capacitor (RC) circuit that activates a detection signal in response to detecting a transient overstress event between the first node and the second node, an active feedback circuit that provides feedback from the first node to the control input of the clamp in response to activation of the detection signal, a second RC circuit that activates a shutdown signal after detecting passage of the transient overstress event based on low pass filtering a voltage difference between the first node and the second node, and a clamp shutdown circuit that turns off the clamp via the control input in response to activation of the shutdown signal.

In accordance with an embodiment, a semiconductor device includes: an n-doped region disposed over an insulating layer; a p-doped region disposed over the insulating layer adjacent to the n-doped region, where an interface between the n-doped region and the p-doped region form a first diode junction; a plurality of segmented p-type anode regions disposed over the insulating layer, each of the plurality of segmented p-type anode regions being surrounded by the n-doped region, where a doping concentration of the plurality of segmented p-type anode regions is greater than a doping concentration of the p-doped region; and a plurality of segmented n-type cathode regions disposed over the insulating layer. Each of the plurality of segmented n-type cathode regions are surrounded by the p-doped region, where a doping concentration of the plurality of segmented n-type cathode regions is greater than a doping concentration of the n-doped region.

An electrostatic discharge (ESD) protection device including: a substrate including: a first, second and third doped regions, the second doped region disposed between the first and third doped regions, the second doped region has a first conductivity type and a first doping concentration and the first and third doped regions have a second conductivity type and a second doping concentration; first and second doped terminal regions disposed within the first and second doped regions, respectively; and a doped island region disposed within the second doped region, the first and second doped terminal regions and doped island region have the second conductivity type and a third doping concentration, the third doping concentration higher than the first and second doping concentrations; and conductive terminals respectively coupled to the doped terminal regions; and an insulation layer arranged on the substrate between the conductive terminals and covering at least the second doped region.

The present disclosure relates to the technical field of semiconductors, and provides an electro-static discharge (ESD) protection structure and a chip. The ESD protection structure includes: a semiconductor substrate, a first P-type well, a first N-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, a second P-type doped portion, a third doped well, a third P-type doped portion and a third N-type doped portion, wherein the first P-type well, the first N-type well and the third doped well are located in the semiconductor substrate; the first N-type doped portion and the first P-type doped portion are located in the first N-type well and spaced apart; the second N-type doped portion and the second P-type doped portion are located in the first P-type well and spaced apart.

This disclosure relates to a semiconductor device including a device with high clamping voltage (HVC device), and an OTS device. Such a semiconductor device provides very advantageous ESD protection. The semiconductor device can be realized in two ways: an OTS device and a device with high clamping voltage can be realized as discrete, independent devices that are combined in one semiconductor package, or an OTS device can be integrated into interconnect layers of a device with high clamping voltage by integration.

A semiconductor device 100 has a power transistor N1 of vertical structure and a temperature detection element 10a configured to detect abnormal heat generation by the power transistor N1. The power transistor N1 includes a first electrode 208 formed on a first main surface side (front surface side) of a semiconductor substrate 200, a second electrode 209 formed on a second main surface side (rear surface side) of the semiconductor substrate 200, and pads 210a-210f positioned unevenly on the first electrode 208. The temperature detection element 10a is formed at a location of the highest heat generation by the power transistor N1, the location (near the pad 210b where it is easiest for current to be concentrated) being specified using the uneven positioning of the pads 210a-210f.

A semiconductor device is provided including a die having an electronic component integrated thereon. The component includes regions in the die, including a first region of a first charge type electrically connected to a first device terminal, a second region of a second charge type forming a first PN junction with the first region, a third region of the first charge type forming a second PN junction with the second region, the third region being spaced apart from the first region by the second region and being electrically connected to the second device terminal, a fourth region of the first charge type forming a third PN junction with the second region, the fourth region being spaced apart from the first region and third region by the second region. The device further includes an electronic unit electrically connected between the first device terminal, the second device terminal and the fourth region.

A bidirectional electrostatic discharge protection device includes a first transient voltage suppressor chip, a second transient voltage suppressor chip, a first conductive wire, and a second conductive wire. The first transient voltage suppressor chip includes a first diode and a first bipolar junction transistor. The first diode and the first bipolar junction transistor are electrically connected to a first pin. The second transient voltage suppressor chip includes a second diode and a second bipolar junction transistor. The second diode and the second bipolar junction transistor are electrically connected to a second pin. The first conductive wire is electrically connected between the first diode and the second bipolar junction transistor. The second conductive wire is electrically connected between the second diode and the first bipolar junction transistor.