In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each other. A first impurity region of the first conductivity type and a second impurity region of the second conductivity type are formed in the first well, and are electrically connected to a first electrode pad. The second impurity region is spaced apart from the first impurity region in a direction of the second well. A third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. A fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated.

A semiconductor device includes a P-type body region and an N-type drift region disposed in a substrate; a gate electrode, disposed on the P-type body region and the N-type drift region, including a high concentration doping region and a high resistance region, wherein a dopant concentration of the high concentration doping region is higher than a dopant concentration of the high resistance region; a spacer disposed on a side of the gate electrode; a highly doped source region disposed in the P-type body region; and a highly doped drain region disposed in the N-type body region. The high concentration doping region overlaps the P-type body region, and the high resistance region overlaps the N-type drift region.

The present disclosure provides an electrostatic discharge protection device, and relates to the technical field of semiconductors. A first P-type heavily-doped region and a first N-type heavily-doped region of the electrostatic discharge protection device are located in a P well, a second P-type heavily-doped region and a third N-type heavily-doped region are located in a first N well, one part of a second N-type heavily-doped region is located in the P well, the other part is located in the first N well, and the P well and the first N well are located in a P-type substrate. The P-type substrate is provided with a gate structure, the gate structure, the first N-type heavily-doped region, and the second N-type heavily-doped region form a transistor, the first N-type heavily-doped region and the gate structure are connected to a first voltage.

The present disclosure provides an electrostatic protection device, and relates to the technical field of semiconductors. The electrostatic discharge protection device includes a first P-type heavily-doped region, a first N-type heavily-doped region, a second N-type heavily-doped region, a second P-type heavily-doped region, and a third N-type heavily-doped region. The first P-type heavily-doped region and the first N-type heavily-doped region are located in a P well, the second P-type heavily-doped region and the third N-type heavily-doped region are located in a first N well, one part of the second N-type heavily-doped region is located in the P well, the other part of the second N-type heavily-doped region is located in first N well, and the P well and the first N well are adjacent to each other and both located in the P-type substrate.

An electrostatic discharge protection circuit includes a pull-down switch, a dummy pattern arranged parallel to the pull-down switch in a first direction, clamp switches arranged parallel to each other in the first direction between the dummy pattern and the pull-down switch, and a resistor configured to transfer a power supply voltage supplied through a power terminal to a gate pattern of the pull-down switch by being arranged parallel to the pull-down switch. Drains of the clamp switches are coupled in common to the power terminal, sources of the clamp switches are coupled in common to a ground terminal, and a first end of the pull-down switch and a second end of the resistor are coupled to each other through a first conductive line extending in the first direction, the pull-down switch, the resistor and the first conductive line are formed in a same layer.

The present invention provides an ESD protection circuit including a control circuit, a first transistor, a filter and a second transistor. The control circuit is configured to detect a level of a supply voltage to generate a control signal. The first transistor is coupled between the supply voltage and a ground voltage, and is used to refer to the control signal to determine whether to be enabled as a discharging path for the supply voltage to discharge current to the ground voltage. The filter is configured to filter the control signal to generate a filtered control signal. The second transistor is coupled between the supply voltage and the ground voltage, and is used to refer to the filtered control signal to determine whether to be enabled as a discharging path for the supply voltage to discharge current to the ground voltage.

A semiconductor device includes first well regions in a substrate and spaced apart from each other, a connection doped region between the first well regions, and a first interconnection line electrically connected to the connection doped region through a first contact. The first well regions and the connection doped region include impurities of a first conductivity type, and a concentration of the impurities in the connection doped region is higher than that in the first well regions. The first well regions extend into the substrate to a depth larger than that of the connection doped region. A first portion of the connection doped region is disposed in the first well regions and a second portion of the connection doped region contacts the substrate.

A MOSFET fabricated in a semiconductor substrate, includes: a gate oxide region formed atop the semiconductor substrate; a gate polysilicon region formed on the gate oxide region; a source region of a first doping type formed in the semiconductor substrate and located at a first side of the gate polysilicon region; and a drain region of the first doping type formed in the semiconductor substrate and located at a second side of the gate polysilicon region. The gate polysilicon region has a first sub-region of the first doping type, a second sub-region of the first doping type, and a third sub-region of a second doping type, wherein the first sub-region is laterally adjacent to the source region, the second sub-region is laterally adjacent to the drain region, and the third sub-region is formed laterally between the first and second sub-regions.

A voltage tracking circuit includes first, second, third and fourth transistors. The first transistor is in a first well, and includes a first gate, a first drain and a first source coupled to a first voltage supply. The second transistor includes a second gate, a second drain and a second source. The second source is coupled to the first drain. The second gate is coupled to the first gate and the pad voltage terminal. The third transistor includes a third gate, a third drain and a third source. The fourth transistor includes a fourth gate, a fourth drain and a fourth source. The fourth drain is coupled to the third source. The fourth source is coupled to the pad voltage terminal. The fourth transistor is in a second well different from the first well, and is separated from the first well in a first direction.

An electrostatic discharge (ESD) protection circuit includes a first transistor, a second transistor, a capacitor, a voltage dividing circuit, and a first diode. The first transistor is coupled between a first power rail and a second power rail. The second transistor is coupled between the first power rail and the second power rail. A bulk of the second transistor is coupled to a control terminal of the first transistor. The capacitor is coupled between the first power rail and a control terminal of the second transistor. The voltage dividing circuit is coupled between the control terminal of the second transistor and the second power rail, and has a divided voltage output terminal coupled to the bulk of the second transistor. The first diode is coupled between the divided voltage output terminal and the second power rail.