Various apparatuses, systems, methods, and media are disclosed to provide over-voltage protection to a data interface of a multi-protocol memory card that includes a first communication interface and a second communication interface that enable communication using different protocols. An interface voltage protection circuit includes a control circuit configured to receive a first supply voltage for operating the first communication interface. The interface voltage protection circuit further includes a pull-down circuit operatively connected with the control circuit, configured to pull down a voltage at a supply voltage rail of the second communication interface such that a voltage at a plurality of connector terminals of the second communication interface is lower than the first supply voltage.

Integrated circuits, such as power amplifier integrated circuits, are disclosed containing compact-footprint, vertically-integrated capacitor-avalanche diode (AD) structures. In embodiments, the integrated circuit includes a semiconductor substrate, a metal layer system, and a vertically-integrated capacitor-AD structure. The metal layer system includes, in turn, a body of dielectric material in which a plurality of patterned metal layers are located. The vertically-integrated capacitor-AD structure includes a first AD formed, at least in part, by patterned portions of the first patterned metal layer. A first metal-insulator-metal (MIM) capacitor is also formed in the metal layer system and at least partially overlaps with the first AD, as taken along a vertical axis orthogonal to the principal surface of the semiconductor substrate. In certain instances, at least a majority, if not the entirety of the first AD vertically overlaps with the first MIM capacitor, by surface area, as taken along the vertical axis.

The present application discloses a semiconductor device, an electronic system and an electrostatic discharge (ESD) protection method for a semiconductor device thereof. The semiconductor device includes a substrate, an operation solder structure disposed on a first surface of the substrate for receiving an operation signal, a detection solder structure disposed on the first surface of the substrate for receiving a chip connection signal, and a semiconductor chip disposed on a second surface of the substrate. The semiconductor chip includes an operation electrical contact coupled to the operation solder structure, a detection electrical contact coupled to the detection solder structure, an ESD protection unit coupled to the operation electrical contact, and a logic circuit coupled to the detection electrical contact for adjusting capacitance of the ESD protection unit according to the chip connection signal.

An electrical fuse (e-fuse) includes a fuse link including a silicided semiconductor layer over a dielectric layer covering a gate conductor. The silicided semiconductor layer is non-planar and extends orthogonally over the gate conductor. A first terminal is electrically coupled to a first end of the fuse link, and a second terminal is electrically coupled to a second end of the fuse link. The fuse link may be formed in the same layer as an intrinsic and/or extrinsic base of a bipolar transistor. The gate conductor may control a current source for programming the e-fuse. The e-fuse reduces the footprint and the required programming energy compared to conventional e-fuses.

In the examples provided herein, an electrostatic discharge (ESD) recording circuit has a first memristive element coupled to a pin of an integrated circuit. The first memristive element switches from a first resistance to a second resistance when an ESD event occurs at the pin, and the first resistance is less than the second resistance. The ESD recording circuit also has shunting circuitry to shunt energy from an additional ESD event away from the first memristive element.

Aspects of the present disclosure are directed to circuitry operable with enhanced capacitance and mitigation of avalanche breakdown. As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves respective transistors of a cascode circuit, one of which controls the other in an off state by applying a voltage to a gate thereof. A plurality of doped regions are separated by trenches, with the conductive trenches being configured and arranged with the doped regions to provide capacitance across the source and the drain of the second transistor, and restricting voltage at one of the source and the drain of the second transistor, therein mitigating avalanche breakdown of the second transistor.

The present disclosure is directed to a semiconductor device and a manufacturing method thereof, which relate to the field of semiconductor technologies. The semiconductor device includes a fin ESD element. The method includes: providing a substrate structure, where the substrate structure includes a semiconductor substrate, and a semiconductor fin for the fin ESD element and an electrode structure surrounding a part of the semiconductor fin that are on the semiconductor substrate; forming a second dielectric layer on the substrate structure to cover the electrode structure; forming, in the second dielectric layer, a trench extending to a top of the electrode, where the trench is on the electrode and extends along a longitudinal direction of the electrode, and a transverse width of the trench is less than or equal to a transverse width of the top of the electrode; and filling the trench with a metal material, so as to form a metal heat sink that is on the top of the electrode and is coupled to the electrode. With the present disclosure, an existing structure of an ESD element is improved, so that a metal heat sink can effectively improve a head dissipation effect of a device, thereby improving a performance of the device.

The present disclosure provides a display substrate and a display device. The display substrate includes a base substrate, and a transistor, an anti-static wire, a first anti-static resistor and a first ground bonding pad on the base substrate, wherein a first terminal of the first anti-static resistor is electrically connected to a first end of the anti-static wire, a second terminal of the first anti-static resistor is electrically connected to the first ground bonding pad, and the first anti-static resistor is at a different layer from a layer at which the anti-static wire is located and a layer at which the first ground bonding pad is located, and is at a same layer as an active layer of the resistor.

An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include electrostatic discharge (ESD) protection circuit structures. The ESD protection circuit structures may be formed in regions other than the region that the IGFETs are formed as well as in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming ESD protection circuit structures in regions below the IGFETs, an older process technology may be used and device size may be decreased. Furthermore, planar IGFETs of FinFETs may be formed in other regions to decrease device size and improve costs.

A method for monitoring a switchable semiconductor component having a protective circuit connected in parallel to the semiconductor component includes tapping an electrical variable applied to the semiconductor component and the protective circuit, and detecting damage to the semiconductor component and/or the protective circuit when an electrical variable is greater than a previously known critical value.