The present disclosure concerns a switching device comprising a first phosphorus-doped silicon layer on top of and in contact with a second arsenic-doped silicon layer. The present disclosure also concerns a method of making a switching device that includes forming a phosphorus-doped silicon layer in an arsenic-doped silicon layer.

The present disclosure concerns a switching device comprising a first phosphorus-doped silicon layer on top of and in contact with a second arsenic-doped silicon layer. The present disclosure also concerns a method of making a switching device that includes forming a phosphorus-doped silicon layer in an arsenic-doped silicon layer.

A power device which is formed on a semiconductor substrate includes: a lateral insulated gate bipolar transistor (LIGBT), a PN diode and a clamp diode. The PN diode is connected in parallel to the LIGBT. The clamp diode has a clamp forward terminal and a clamp reverse terminal, which are electrically connected to a drain and a gate of the LIGBT, to clamp a gate voltage applied to the gate not to be higher than a predetermined voltage threshold.

The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure (ESD device) includes: a bipolar transistor comprising a collector region, an emitter region and a base region; and a lateral ballasting resistance comprising semiconductor material adjacent to the collector region.

Embodiment provides an integrated circuit latch-up test structure. The circuit includes: a first P-type heavily doped region, a first N-type heavily doped region, a second P-type heavily doped region, and a second N-type heavily doped region. A first distance is provided between the first P-type heavily doped region and the first N-type heavily doped region, a second distance is provided between the first N-type heavily doped region and the second P-type heavily doped region, and a third distance is provided between the second P-type heavily doped region and the second N-type heavily doped region. The test structure is configured to test electrical parameters of a latch-up effect of an integrated circuit corresponding to the test structure by adjusting at least one of the first distance, the second distance, and the third distance.

A power device which is formed on a semiconductor substrate includes: a lateral insulated gate bipolar transistor (LIGBT), a PN diode and a clamp diode. The PN diode is connected in parallel to the LIGBT. The clamp diode has a clamp forward terminal and a clamp reverse terminal, which are electrically connected to a drain and a gate of the LIGBT, to clamp a gate voltage applied to the gate not to be higher than a predetermined voltage threshold.

An inverter logic circuit includes a bipolar junction transistor and a zener diode. The zener diode is connected between the base of the bipolar junction transistor and ground (or other reference voltage). The zener diode is reverse biased such that a leakage current through the zener diode allows for sufficient current through the emitter-base terminals of the bipolar junction transistor when a voltage is applied across the emitter and base terminals of the bipolar junction transistor to turn the transistor ON in the absence of an external signal to the base. As such the bipolar junction transistor functions as a normally ON bipolar junction transistor.

The present disclosure concerns a switching device comprising a first phosphorus-doped silicon layer on top of and in contact with a second arsenic-doped silicon layer. The present disclosure also concerns a method of making a switching device that includes forming a phosphorus-doped silicon layer in an arsenic-doped silicon layer.

An inverter logic circuit includes a bipolar junction transistor and a zener diode. The zener diode is connected between the base of the bipolar junction transistor and ground (or other reference voltage). The zener diode is reverse biased such that a leakage current through the zener diode allows for sufficient current through the emitter-base terminals of the bipolar junction transistor when a voltage is applied across the emitter and base terminals of the bipolar junction transistor to turn the transistor ON in the absence of an external signal to the base. As such the bipolar junction transistor functions as a normally ON bipolar junction transistor.

An inverter logic circuit includes a bipolar junction transistor and a zener diode. The zener diode is connected between the base of the bipolar junction transistor and ground (or other reference voltage). The zener diode is reverse biased such that a leakage current through the zener diode allows for sufficient current through the emitter-base terminals of the bipolar junction transistor when a voltage is applied across the emitter and base terminals of the bipolar junction transistor to turn the transistor ON in the absence of an external signal to the base. As such the bipolar junction transistor functions as a normally ON bipolar junction transistor.