Patent classifications
H01L27/1281
Method of manufacturing thin film transistor and display device including polishing capping layer coplanar with active layer
A thin film transistor includes an active layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, a capping layer filling a thickness difference between the first portion and the second portion and arranged on the first portion, a gate insulating layer arranged on the capping layer, a gate electrode on the active layer, wherein the gate insulating layer and the capping layer are disposed between the gate electrode and the active layer, and a source electrode and a drain electrode connected to the active layer.
Display substrate, display apparatus and manufacturing method of display substrate
A display substrate, a display apparatus, and a manufacturing method of the display substrate are provided. The display substrate includes: a base substrate; and a crystallization induction layer and a polysilicon layer stacked on the base substrate. The crystallization induction layer includes induction layer patterns and intervals between the induction layer patterns. The polysilicon layer includes a portion overlapping the induction layer patterns and a portion overlapping the intervals, a crystallinity of the portion of the polysilicon layer overlapping the induction layer patterns is larger than a crystallinity of the portion of the polysilicon layer overlapping the intervals.
DISPLAY DEVICE
A display device according to an aspect of the disclosure includes a display region. The display region is provided with a plurality of first grooves and a plurality of second grooves formed between adjacent control lines and spaced apart from the plurality of control lines, in a plan view. Each of the plurality of first grooves extends in a second direction along a coupling semiconductor layer, between the adjacent control lines, in a plan view. Each of the plurality of second grooves extends in a direction intersecting a first groove of the plurality of first grooves, and is adjacent to at least one end portion of the first groove.
CRYSTALLINE P-TYPE SEMICONDUCTOR FILM AND THIN FILM TRANSISTOR AND DIODE AND ELECTRONIC DEVICE
Disclosed are a crystalline p-type semiconductor film having a plurality of crystal grains with an average grain size of submicron and including a tin-doped copper halide, and a semiconductor device, a thin film transistor, a diode, and an electronic device including the same.
DISPLAY DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS
There is provided a display device including: a light emitting element; and a drive transistor (DRTr) that includes a coupling section (W1) and a plurality of channel sections (CH) coupled in series through the coupling section (W1), wherein the drive transistor (DRTr) is configured to supply a drive current to the light emitting element.
METHOD FOR PRODUCING A SEMICONDUCTOR CHIP AND SEMICONDUCTOR CHIP
A method for producing a semiconductor chip (100) is provided, in which, during a growth process for growing a first semiconductor layer (1), an inhomogeneous lateral temperature distribution is created along at least one direction of extent of the growing first semiconductor layer (1), such that a lateral variation of a material composition of the first semiconductor layer (1) is produced. A semiconductor chip (100) is additionally provided.
THIN FILM TRANSISTOR AND PREPARATION METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY APPARATUS
A thin film transistor and a preparation method thereof, an array substrate and a display apparatus are provided. The preparation method includes an operation of forming a low temperature poly silicon active layer; a substrate has a first region and a second region; and the step includes: forming a buffer layer on the first region and the second region of the substrate, the buffer layer having a thickness at a portion corresponding to the first region greater than that at a portion corresponding to the second region; or, forming the buffer layer on the first region of the substrate; forming an amorphous silicon layer on the buffer layer; performing laser crystallization processing on the amorphous silicon layer so as to convert the amorphous silicon layer into a poly silicon layer; and removing the poly silicon layer on the second region, and forming the low temperature poly silicon active layer on the first region.
Thin film transistor, method for fabricating the same, and array substrate
Embodiments of the present invention provide a thin film transistor, a method for fabricating the same and an array substrate. The thin film transistor comprises a base substrate and an active region and a plurality of reflective plates formed on the base substrate, wherein the plurality of reflective plates are spaced apart from each other and provided at least at positions corresponding to the active region, the active region comprises polysilicon, and the polysilicon in the active region is formed by irradiating an amorphous silicon layer with laser emitted from a side of the amorphous silicon layer away from the reflective plates.
THIN FILM TRANSISTOR, MANUFACTURING PROCESS FOR THIN FILM TRANSISTOR, AND LASER ANNEALING APPARATUS
The present invention provides a thin film transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer, which are laminated on a substrate. The semiconductor layer is a polysilicon thin film. The polysilicon thin film in regions corresponding to the source electrode and the drain electrode has a smaller crystal grain size than that of the polysilicon thin film in a channel region between the source electrode and the drain electrode.
Thin film transistor and a manufacturing method thereof, array substrate and a manufacturing method thereof, display device
A thin film transistor and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display device are disclosed. The manufacturing method of the array substrate includes depositing an amorphous silicon thin film layer on a base substrate; performing a patterning process on the amorphous silicon thin film layer, so as to form a pattern with multiple small pores at a surface of the amorphous silicon thin film layer. With this method, when a laser annealing treatment of amorphous silicon is performed, the molten silicon after melting fills the space of small pores at a surface of the amorphous silicon thin film layer firstly, thereby avoiding forming a protruded grain boundary that is produced because the excess volume of polysilicon is squeezed.