Techniques are described for implementing a split-select-block (split-SEL) complementary metal-oxide semiconductor (CMOS) image sensor (CIS) pixel physical architecture, such as for reducing noise in low-light application contexts. The split-SEL CIS pixel physical architecture can include a pixel block with one or more photodiodes. Above the photodiodes, there can be: a first oxide diffusion region with a reset block and a gain block disposed thereon; and a second oxide diffusion region with a select block disposed thereon. Below the photodiodes, there can be a third oxide diffusion region with a source follower (SF) block (e.g., a square-gate SF transistor) disposed thereon. A trace can be routed through the set of photodiodes to couple the source of the SF block with the select block. The architecture permits an appreciable increase in the physical gate length and/or other features.

A pixel includes a workpiece having a protrusion and a bulk, wherein the protrusion extends from an upper surface of the bulk. The pixel further includes a floating diffusion node in the protrusion. The pixel further includes a gate structure over the bulk, wherein a top surface of the gate structure is above a top surface of the floating diffusion node. The pixel further includes a photosensitive device in the bulk. The pixel further includes an isolation well surrounding the photosensitive device.

An image sensing device includes a photoelectric conversion element, a floating diffusion (FD) region, and a transfer gate. The photoelectric conversion element is disposed in a substrate, and generates photocharges in response to incident light. The floating diffusion (FD) region is disposed over the photoelectric conversion element, and stores the photocharges generated by the photoelectric conversion element. The transfer gate transfer the photocharges generated by the photoelectric conversion element to the floating diffusion (FD) region in response to a transmission signal. The transfer gate includes a horizontal gate disposed over the photoelectric conversion element, and a vertical gate coupled to the horizontal gate. The vertical gate is positioned at a side of the photoelectric conversion element, and surrounds the photoelectric conversion element.

Aspects of the technology described herein relate to improved semiconductor-based image sensor designs. In some embodiments, an integrated circuit may comprise a photodetection region and a drain region electrically coupled to the photodetection region, and the photodetection region may be configured to induce an intrinsic electric field in a direction from the photodetection region to the drain region(s). In some embodiments, an integrated circuit may comprise a plurality of pixels and a control circuit configured to control a transfer of charge carriers in a plurality of time-binning pixels. In some embodiments, an optical component for optical rejection is provided in between a waveguide and the time-binning pixel and configured to block at least some excitation photons in a pulsed light stream from arriving at the photodetection region. In some embodiments, the time-binning pixel does not comprise a time-gated transistor for electronic rejection configured to block a transfer of charge carriers associated with excitation photons in the pulsed light stream.

Transistors include trenches formed in the semiconductor substrate having a first conductive type. The trenches define, in a channel width plane of the transistor, at least one nonplanar substrate structure having a plurality of sidewall portions and a tip portion disposed between the plurality of sidewall portions. An epitaxial overlayer is epitaxially grown on the sidewall portions and the tip portion. A channel doping layer having a doped portion of the semiconductor substrate is formed in the nonplanar substrate structure and enclosed by the epitaxial overlayer. An isolation layer is disposed in the trenches and over the epitaxial overlayer. A gate is disposed on the isolation layer and extends into the trenches.

A semiconductor device includes a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor connected to an output node of the first PMOS and NMOS transistors. The first PMOS transistor includes first nanowires, first source and drain regions on opposite sides of each first nanowire, and a first gate completely surrounding each first nanowire. The first NMOS transistor includes second nanowires, second source and drain regions on opposite sides of each second nanowire, and a second gate extending from the first gate and completely surrounding each second nanowire. The second NMOS transistor includes third nanowires, third source and drain regions on opposite sides of each third nanowire, and a third gate, separated from the first and second gates, and completely surrounding each third nanowire. A number of third nanowires is greater than that of first nanowires. The first and second gates share respective first and second nanowires.

An imaging device connected to a neural network is provided. An imaging device having a neuron in a neural network includes a plurality of first pixels, a first circuit, a second circuit, and a third circuit. Each of the plurality of first pixels includes a photoelectric conversion element. The plurality of first pixels is electrically connected to the first circuit. The first circuit is electrically connected to the second circuit. The second circuit is electrically connected to the third circuit. Each of the plurality of first pixels generates an input signal of the neuron. The first circuit, the second circuit, and the third circuit function as the neuron. The third circuit includes an interface connected to the neural network.

A pixel cell includes a nitrogen-implanted region at a semiconductor material-gate oxide proximate interface located in a region above a photodiode. The pixel cell is further devoid of implanted nitrogen in channel regions of a plurality of pixel transistors. Thus, Si—N bonds are formed at the semiconductor material-gate oxide interface in the region above the photodiode, while the channel regions are protected from nitrogen implantation at the semiconductor material-gate oxide interface. Methods of forming the pixel cell are also described.

Pixels, such as for image sensors and electronic devices, include a photodiode formed in a semiconductor substrate, a floating diffusion, and a transfer structure selectively coupling the photodiode to the floating diffusion. The transfer structure includes a transfer gate formed on the semiconductor substrate, and a vertical channel structure including spaced apart first doped regions formed in the semiconductor substrate between the transfer gate and the photodiode. Each spaced apart first doped region is doped at a first dopant concentration with a first-type dopant. The spaced apart first doped regions are formed in a second doped region doped at a second dopant concentration with a second-type dopant of a different conductive type.

A method for forming a pixel includes forming, in a semiconductor substrate, a wide trench having an upper depth with respect to a planar top surface of the semiconductor substrate. The method also includes ion-implanting a floating-diffusion region between the planar top surface and a junction depth in the semiconductor substrate. In a cross-sectional plane perpendicular to the planar top surface, the floating-diffusion region has (i) an upper width between the planar top surface and the upper depth, and (ii) between the upper depth and the junction depth, a lower width that exceeds the upper width. Part of the floating-diffusion region is beneath the wide trench and between the upper depth and the junction depth.