Decoupling structures are provided. The decoupling structures may include first conductive patterns, second conductive patterns and a unitary supporting structure that structurally supports the first conductive patterns and the second conductive patterns. The decoupling structures may also include a common electrode disposed between ones of the first conductive patterns and between ones of the second conductive patterns. The first conductive patterns and the common electrode are electrodes of a first capacitor, and the second conductive patterns and the common electrode are electrodes of a second capacitor. The unitary supporting structure may include openings when viewed from a plan perspective. The first conductive patterns and the second conductive patterns are horizontally spaced apart from each other with a separation region therebetween, and none of the openings extend into the separation region.

A polysilicon-insulator-polysilicon (PIP) structure includes: a first polysilicon region formed on a substrate; a first insulation region formed outside one side of the first polysilicon region and adjoined to the first polysilicon region in a horizontal direction; and a second polysilicon region formed outside one side of the first insulation region. The first polysilicon region, the first insulation region and the second polysilicon region are adjoined in sequence in the horizontal direction. The second polysilicon region is formed outside the first insulation region by a first self-aligned process step, and the first insulation region is formed outside the first polysilicon region by a second self-aligned process step.

A method for manufacturing a capacitor array includes: providing a substrate provided with a device area configured for forming a capacitor and a peripheral area located at a periphery of the device area; forming successively a first support layer and a first sacrificial layer on the substrate; etching the first sacrificial layer of the peripheral area to expose the first support layer, so as to form a first via; and filling the first via to form a support pillar.

A method of forming a semiconductor structure including a metal-insulator-metal (MIM) capacitor includes: forming a stack structure over a substrate, wherein the stack structure includes a plurality of electrode material layers and a plurality of insulating material layers alternately stacked over the substrate; forming a mask layer on the stack structure; and performing a patterning process on the stack structure, so as to form the MIM capacitor comprising alternately stacked electrodes and insulating layers. Performing the patterning process includes: performing a first etching process to remove a first portion of the stack structure exposed by the mask layer; performing a first trimming process on the mask layer to remove a portion of the mask layer, and a first trimmed mask layer is formed; and performing a second etching process to remove a second portion of the stack structure exposed by the first trimmed mask layer.

The present application discloses a semiconductor device with a horizontally arranged capacitor. The semiconductor device includes a first palm portion positioned above a substrate; a second palm portion positioned above the substrate and opposite to the first palm portion; a first finger portion arranged substantially in parallel with a main surface of the substrate, positioned between the first palm portion and the second palm portion, and connecting to the first palm portion; a second finger portion arranged substantially in parallel with the first finger portion, positioned between the first palm portion and the second palm portion, and connecting to the second palm portion; a capacitor insulation layer positioned between the first finger portion and the second finger portion; a first spacer positioned between the first palm portion and second finger portion; and a second spacer positioned between the second palm portion and the first finger portion.

A method of operating a mechanical switching device is disclosed. The switching device includes a housing, an assembly disposed in the housing, and a body. The assembly is thermally deformable and comprises a beam held in two different places by two arms secured to edges of the housing. The beam is remote from the body in a first configuration and in contact with and immobilized by the body in a second configuration. The assembly has the first configuration at a first temperature and the second configuration when one of the arms has a second temperature different from the first temperature. The method includes exposing an arm of the assembly to the second temperature, and releasing the beam using a release mechanism. The release mechanism includes a pointed element comprising a pointed region directed towards the body. The pointed element limits an open crater in a concave part of a projection.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first palm portion positioned above a substrate; a second palm portion positioned above the substrate and opposite to the first palm portion; a first finger portion arranged substantially in parallel with a main surface of the substrate, positioned between the first palm portion and the second palm portion, and connecting to the first palm portion; a second finger portion arranged substantially in parallel with the first finger portion, positioned between the first palm portion and the second palm portion, and connecting to the second palm portion; a capacitor insulation layer positioned between the first finger portion and the second finger portion; a first spacer positioned between the first palm portion and second finger portion; and a second spacer positioned between the second palm portion and the first finger portion.

A digital integrated circuit includes first areas of a substrate which incorporate digital functions and second areas of the substrate which are filler between first areas. A capacitance is provided by interdigitated metal-insulator-metal structures formed from a metallization level above the substrate. The structures of the capacitance are vertically aligned with one or more of the second areas.

A semiconductor device including a first pad on a substrate extending in a first direction and a second direction, a lower electrode connected to and disposed on the first pad, first to third supporter layers disposed on a side wall of the lower electrode and sequentially spaced apart from each other in a third direction perpendicular to the first direction and the second direction, a dielectric film disposed on the lower electrode and the first to third supporter layers, and an upper electrode disposed on the dielectric film. At least one of a side wall of the lower electrode between the first supporter layer and the second supporter layer, and a side wall of the lower electrode between the second supporter layer and the third supporter layer includes a first portion including protrusions extending in the first direction and includes a second portion including no protrusions.

A capacitor structure includes a first metal structure, a second metal structure, and a dielectric material. The second metal structure is disposed below the first metal structure. Each of the first metal structure and the second metal structure includes at least three conductive components. The conductive components have a fish-bone shape. The dielectric material is disposed in a plurality of isolators of the first metal structure, in a plurality of isolators of the second metal structure, and between the first metal structure and the second metal structure.