A gate-turn-off thyristor is provided. The gate-turn-off thyristor includes a plurality of strips formed by repeatedly arranging a plurality of N-type emitter regions with high doping concentration of an upper transistor on an upper surface of an N-type silicon substrate with high resistivity, wherein a periphery of each strip of the plurality of strips is surrounded with a P-type dense base region bus bar of the upper transistor, a cathode metal layer is disposed on an N-type emitter region of the plurality of N-type emitter regions of the upper transistor, and a P-type base region of the upper transistor is disposed below the N-type emitter region of the upper transistor; a side of the P-type base region of the upper transistor is connected to a P-type dense base region of the upper transistor or a P-type dense base region bus bar of the upper transistor.

An npnp layered switch is modified to have a composite anode structure. Instead of the continuous p-type bottom anode layer of a typical npnp IGTO device, thyristor, or IGBT, the composite anode is formed of a segmented p-type layer with gaps containing n-type semiconductor material. The n-type material forms a majority carrier path between the bottom anode electrode and the n-type collector of the vertical npn bipolar transistor. When a trenched gate is biased high, the majority carrier path is created between the bottom anode electrode and the top cathode electrode. Such a current path operates at very low operating voltages, starting at slightly above 0 volts. Above operating voltages of about 1.0 volts, the npnp layered switch operates normally and uses regenerative bipolar transistor action to conduct a vast majority of the current. The two current paths conduct in parallel.

An npnp layered switch is modified to have a composite anode structure. Instead of the continuous p-type bottom anode layer of a typical npnp IGTO device, thyristor, or IGBT, the composite anode is formed of a segmented p-type layer with gaps containing n-type semiconductor material. The n-type material forms a majority carrier path between the bottom anode electrode and the n-type collector of the vertical npn bipolar transistor. When a trenched gate is biased high, the majority carrier path is created between the bottom anode electrode and the top cathode electrode. Such a current path operates at very low operating voltages, starting at slightly above 0 volts. Above operating voltages of about 1.0 volts, the npnp layered switch operates normally and uses regenerative bipolar transistor action to conduct a vast majority of the current. The two current paths conduct in parallel.

A short-circuit semiconductor component comprises a semiconductor body, in which a rear-side base region of a first conduction type, an inner region of a second complementary conduction type, and a front-side base region of the first conduction type are disposed. The rear-side base region is electrically connected to a rear-side electrode, and the front-side base region is electrically connected to a front-side electrode. A turn-on structure, which is an emitter structure of the second conduction type, is embedded into the front-side base region and/or rear-side base region and is covered by the respective electrode and is electrically contacted with the electrode placed on the base region respectively embedding it. It can be turned on by a trigger structure which can be activated by an electrical turn-on signal. In the activated state, the trigger structure injects an electrical current surge into the semiconductor body, which irreversibly destroys a semiconductor junction.

A short-circuit semiconductor component comprises a semiconductor body, in which a rear-side base region of a first conduction type, an inner region of a second conduction type complementary to the first conduction type, and a front-side base region of the first conduction type are disposed. The rear-side base region is electrically connected to a rear-side electrode with a rear-side electrode width, and the front-side base region is electrically connected to a front-side electrode with a front-side electrode width. A turn-on structure with a turn-on structure width is embedded into the front-side and/or rear-side base region and is covered by the respective electrode. The turn-on structure is configured to be turned on depending on a supplied turn-on signal and to produce, on a one-off basis, an irreversible, low-resistance connection between the two electrodes. The ratio of the turn-on structure width to the respective electrode width is less than 1.

A semiconductor device includes a conductive substrate, a conductive first joint portion arranged on the substrate, a SiC diode chip arranged on the first joint portion, a conductive second joint portion arranged on the SiC diode chip, and a transistor chip arranged on the second joint portion. The SiC diode chip includes a cathode pad arranged on one end and an anode pad arranged on the other end in the thickness direction. The cathode pad is joined to the substrate by the first joint portion. The transistor chip includes a drain electrode arranged on one end in the thickness direction. The anode pad is joined with the drain electrode by the second joint portion. The anode pad is arranged in a region enclosed by an outer edge of the SiC diode chip as viewed in a thickness direction of the substrate. The anode pad has an area larger than that of the transistor chip as viewed in the thickness direction of the substrate.

A semiconductor device includes a semiconductor layer having a first principal surface on one side thereof and a second principal surface on the other side thereof, a channel region of a first conductivity type formed at a surface layer portion of the first principal surface of the semiconductor layer, an emitter region of a second conductivity type formed at a surface layer portion of the channel region in the semiconductor layer, a drift region of the second conductivity type formed in a region of the second principal surface side with respect to the channel region in the semiconductor layer so as to be electrically connected to the channel region, a collector region of the first conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region, a cathode region of the second conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region and including a continuously laid around line-shaped pattern, and a gate electrode formed at the first principal surface side of the semiconductor layer so as to face the channel region across an insulating film.

A diode includes an anode electrode layer; a cathode electrode layer; a buffer layer of a first conductivity type formed between the anode electrode layer and the cathode electrode layer in a region extending to a location at a distance of 30 μm or more from the cathode electrode layer; a first semiconductor layer of the first conductivity type formed in a region between the anode electrode layer and the cathode electrode layer, and being in contact with the buffer layer of the first conductivity type; and a second semiconductor layer of a second conductivity type formed in a region between the anode electrode layer and the first semiconductor layer of the first conductivity type. The carrier concentration in the first semiconductor layer is lower than the carrier concentration in the buffer layer. The carrier concentration in the buffer layer is less than 1×10.sup.15 cm.sup.−3.

A triac has a vertical structure formed from a silicon substrate having an upper surface side. A main metallization on the upper surface side has a first portion resting on a first region of a first conductivity type formed in a layer of a second conductivity type. A second portion of the main metallization rests on a portion of the layer. A gate metallization on the upper surface side rests on a second region of the first conductivity type formed in the layer in the vicinity of the first region. A porous silicon bar formed in the layer at the upper surface side has a first end in contact with the gate metallization and a second end in contact with the main metallization.

A thyristor device that can include a disc-shaped device comprising a semiconductor material forming alternating p-n-p-n type layers. The device can include a gate area extending from an external gate lead contact point to a plurality of thyristor units connected in parallel. Each thyristor unit can include at least one exposed pB layer portion to form at least one plural point to which gate current can be directed. Further, an insulator layer can be formed over the gate area to insulate at least a portion of the gate electrode from the pB layer so that displacement current can be directed to short dots and then to the plural points. Current entering each thyristor unit can generate a turned-on area at each thyristor unit that spreads throughout the thyristor device.