A high electron mobility transistor includes: a first semiconductor layer over a substrate, and a second semiconductor layer over the first semiconductor layer, the second semiconductor layer having a band gap discontinuity with the first semiconductor layer, and at the first semiconductor layer and/or the second conductive layer includes indium. A top layer is over the second semiconductor layer, and a metal layer is over, and extends into, the top layer, the top layer separating the metal layer from the second semiconductor layer. A gate electrode is over the top layer, a third semiconductor layer being between the gate electrode and the top layer, where a sidewall of the third semiconductor layer and a sidewall of the metal layer are separated. A source and drain are on opposite sides of the gate electrode, the top layer extending continuously from below the source, below the gate electrode, and below the drain.

There is provided a semiconductor element containing gallium nitride. The semiconductor element includes a semiconductor layer including a first surface having a first region and a second region that is a projecting portion having a strip shape and projecting relative to the first region or a recessed portion having a strip shape and being recessed relative to the first region. Of the first surface, at least one of surfaces of the first region and the second region includes a crystal plane having a plane orientation different from a (000-1) plane orientation and a (1-100) plane orientation.

A semiconductor transistor structure with reduced contact resistance includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a two-dimensional electron gas (2DEG) layer at an interface between the barrier layer and the channel layer, and a recess in a contact region. The recess penetrates through the barrier layer and extends into the channel layer. An Ohmic contact metal is disposed in the recess. The Ohmic contact metal is in direct contact with a vertical side surface of the barrier layer in the recess and in direct contact with an inclined side surface of the 2DEG layer and the channel layer in the recess.

A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional “2D” semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.

A high electron mobility transistor (HEMT) includes a substrate; and a first semiconductor layer over the substrate. The HEMT further includes a second semiconductor layer over the first semiconductor layer, wherein the second semiconductor layer has a band gap discontinuity with the first semiconductor layer, and at least one of the first semiconductor layer or the second semiconductor layer comprises indium. The HEMT further includes a top layer over the second semiconductor layer. The HEMT further includes a gate electrode over the top layer. The HEMT further includes a source and a drain on opposite sides of the gate electrode, wherein the top layer extends continuously from below the source, below the gate electrode, and to below the drain.

An ohmic contact for a multiple channel FET comprises a plurality of slit-shaped recesses in a wafer on which a multiple channel FET resides, with each recess having a depth at least equal to the depth of the lowermost channel layer. Ohmic metals in and on the sidewalls of each recess provide ohmic contact to each of the multiple channel layers. An ohmic metal-filled linear connecting recess contiguous with the outside edge of each recess may be provided, as well as an ohmic metal contact layer on the top surface of the wafer over and in contact with the ohmic metals in each of the recesses. The present ohmic contact typically serves as a source and/or drain contact for the multiple channel FET. Also described is the use of a regrown material to make ohmic contact with multiple channels, with the regrown material preferably having a corrugated structure.

A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional “2D” semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.

Embodiments of the invention provide a method of forming a group III-V material utilized in thin film transistor devices. In one embodiment, a gallium arsenide based (GaAs) layer with or without dopants formed from a solution based precursor may be utilized in thin film transistor devices. The gallium arsenide based (GaAs) layer formed from the solution based precursor may be incorporated in thin film transistor devices to improve device performance and device speed. In one embodiment, a thin film transistor structure includes a gate insulator layer disposed on a substrate, a GaAs based layer disposed over the gate insulator layer, and a source-drain metal electrode layer disposed adjacent to the GaAs based layer.

A semiconductor device includes an electrode material diffusion suppression layer provided either between a gate electrode and a gate insulation film, between Al-containing ohmic electrodes and an Au interconnection, and below the gate electrode and above the Al-containing ohmic electrodes, the electrode material diffusion suppression layer having a structure wherein a first the TaN layer, a Ta layer, and a second the TaN layer are stacked in sequence.

A display substrate including a base substrate, a first thin film transistor disposed on the base substrate and including a first gate electrode and a first semiconductor active layer; a second thin film transistor electrically connected to the first thin film transistor, the second thin film transistor including a second gate electrode and a second semiconductor active layer; and an organic light emitting device electrically connected to the second thin film transistor. The first semiconductor active layer includes a first material and the second semiconductor active layer includes a second material different from the first material.