A method for producing an ohmic contact on a crystallographic C-side of a silicon carbide substrate. The method includes: applying a layer stack to the crystallographic C-side of the silicon carbide substrate, the layer stack including at least one semiconducting layer containing germanium, and at least one metallic layer; and producing a point-by-point liquid phase of the layer stack, a surface of the layer stack being scanned using laser beams.

A diode is formed by a polycrystalline silicon bar which includes a first doped region with a first conductivity type, a second doped region with a second conductivity type and an intrinsic region between the first and second doped regions. A conductive layer extends parallel to the polycrystalline silicon bar and separated from the polycrystalline silicon bar by a dielectric layer. The conductive layer is configured to be biased by a bias voltage.

It is an object of the present invention to form a pixel electrode and a metal film using one resist mask in manufacturing a stacked structure by forming the metal film over the pixel electrode. A conductive film to be a pixel electrode and a metal film are stacked. A resist pattern having a thick region and a region thinner than the thick region is formed over the metal film using an exposure mask having a semi light-transmitting portion. The pixel electrode, and the metal film formed over part of the pixel electrode to be in contact therewith are formed using the resist pattern. Accordingly, a pixel electrode and a metal film can be formed using one resist mask.

It is an object of the present invention to connect a wiring, an electrode, or the like formed with two incompatible films (an ITO film and an aluminum film) without increasing the cross-sectional area of the wiring and to achieve lower power consumption even when the screen size becomes larger. The present invention provides a two-layer structure including an upper layer and a lower layer having a larger width than the upper layer. A first conductive layer is formed with Ti or Mo, and a second conductive layer is formed with aluminum (pure aluminum) having low electric resistance over the first conductive layer. A part of the lower layer projected from the end section of the upper layer is bonded with ITO.

A method of manufacturing, with high mass productivity, liquid crystal display devices having highly reliable thin film transistors with excellent electric characteristics is provided. In a liquid crystal display device having an inverted staggered thin film transistor, the inverted staggered thin film transistor is formed as follows: a gate insulating film is formed over a gate electrode; a microcrystalline semiconductor film which functions as a channel formation region is formed over the gate insulating film; a buffer layer is formed over the microcrystalline semiconductor film; a pair of source and drain regions are formed over the buffer layer; and a pair of source and drain electrodes are formed in contact with the source and drain regions so as to expose a part of the source and drain regions.

Embodiments of the present disclosure provide a thin film transistor, a method for manufacturing a thin film transistor, an array substrate, a display panel, and a display device. The thin film transistor includes: a base substrate; an active layer, an insulating layer, and a source-drain layer sequentially stacked on the base substrate, wherein the source-drain layer is electrically connected to the active layer through a via hole penetrating the insulating layer; and a transition layer arranged between the source-drain layer and the active layer at a position of the via hole, wherein the transition layer covers a bottom of the via hole and covers at least part of a sidewall of the via hole, and the transition layer comprises elements of the active layer and elements of a part of the source-drain layer, the part of the source-drain layer being in contact with the transition layer.

A semiconductor device, a manufacturing method thereof, and a display panel are provided. The semiconductor device includes a first active component. The first active component includes a first semiconductor layer and a contact layer. The contact layer includes a first doped layer, a second semiconductor layer, and a second doped layer stacked from bottom to top, so that there are at least two PN junction interfaces inside to increase a light to dark current ratio of the semiconductor device.

A display module and a method for manufacturing the same are provided. The display module manufacturing method includes: forming a semiconductor pattern on a substrate; forming a first insulating layer covering the semiconductor pattern on the substrate; forming a gate electrode on a region of the first insulating layer corresponding to a gate region of the semiconductor pattern; forming a second insulating layer covering the gate electrode on the first insulating layer; forming a first hole passing through the first insulating layer and the second insulating layer to expose a drain region of the semiconductor pattern and forming a second hole passing through the first insulating layer and the second insulating layer to expose a source region of the semiconductor pattern; and forming a first barrier pattern on the drain region in the first hole and a second barrier pattern on the source region in the second hole, and forming a drain electrode on the first barrier pattern and a source electrode on the second barrier pattern.

The present technology provides a semiconductor device. The semiconductor device includes a stack including insulating patterns and conductive patterns stacked alternately with each other, a channel layer including a first channel portion protruding out of the stack and a second channel portion in the stack, and passing through the stack, and a conductive line surrounding the first channel portion, and the first channel portion includes metal silicide.

A semiconductor structure is provided, and the semiconductor structure includes a substrate, and an active area is defined thereon, a gate structure spanning the active area, wherein the overlapping range of the gate structure and the active area is defined as an overlapping region, and the overlapping region includes four corners, and at least one salicide block covering the four corners of the overlapping region.