A semiconductor device includes a substrate including a first main surface; a semiconductor layer provided on the first main surface of the substrate; an electrically insulating layer provided on the semiconductor layer; a source electrode and a drain electrode that are provided on the semiconductor layer; and a gate electrode provided on the electrically insulating layer. The semiconductor layer has an electron transport layer provided on the substrate and including a first upper surface, and has an electron supply layer provided on the electron transport layer. A first opening and a second opening are each formed in the electron supply layer and the electron transport layer. A third opening connected to the first opening and a fourth opening connected to the second opening are each formed in the electrically insulating layer.

There is disclosed the integration of a Schottky diode with a MOSFET, more in detail there is a free-wheeling Schottky diode and a power MOSFET on top of a buried grid material structure. Advantages of the specific design allow the whole surface area to be used for MOSFET and Schottky diode structures, the shared drift layer is not limited by Schottky diode or MOSFET design rules and therefore, one can decrease the thickness and increase the doping concentration of the drift layer closer to a punch through design compared to the state of the art. This results in higher conductivity and lower on-resistance of the device with no influence on the voltage blocking performance. The integrated device can operate at higher frequency. The risk for bipolar degradation is avoided.

There is disclosed the integration of a Schottky diode with a MOSFET, more in detail there is a free-wheeling Schottky diode and a power MOSFET on top of a buried grid material structure. Advantages of the specific design allow the whole surface area to be used for MOSFET and Schottky diode structures, the shared drift layer is not limited by Schottky diode or MOSFET design rules and therefore, one can decrease the thickness and increase the doping concentration of the drift layer closer to a punch through design compared to the state of the art. This results in higher conductivity and lower on-resistance of the device with no influence on the voltage blocking performance. The integrated device can operate at higher frequency. The risk for bipolar degradation is avoided.

A trench-type MESFET includes an n-type semiconductor layer including a Ga.sub.2O.sub.3-based single crystal and including plural trenches opening on one surface, first insulators respectively buried in bottom portions of the plural trenches, gate electrodes respectively buried in the plural trenches so as to be placed on the first insulators and so that side surfaces thereof are in contact with the n-type semiconductor layer, a source electrode connected to a mesa-shaped portion between the adjacent trenches of the n-type semiconductor layer, second insulators respectively buried in the plural trenches so as to be placed on the gate electrodes to insulate the gate electrodes and the source electrode, and a drain electrode directly or indirectly connected to the n-type semiconductor layer on a side opposite to the source electrode.

A trench-type MESFET includes an n-type semiconductor layer including a Ga.sub.2O.sub.3-based single crystal and including plural trenches opening on one surface, first insulators respectively buried in bottom portions of the plural trenches, gate electrodes respectively buried in the plural trenches so as to be placed on the first insulators and so that side surfaces thereof are in contact with the n-type semiconductor layer, a source electrode connected to a mesa-shaped portion between the adjacent trenches of the n-type semiconductor layer, second insulators respectively buried in the plural trenches so as to be placed on the gate electrodes to insulate the gate electrodes and the source electrode, and a drain electrode directly or indirectly connected to the n-type semiconductor layer on a side opposite to the source electrode.

A method for manufacturing nitride semiconductor device includes a second step of forming, on a gate layer material film, a gate electrode film that is a material film of a gate electrode, a third step of selectively etching the gate electrode film to form the gate electrode 22 of a ridge shape, and a fourth step of selectively etching the gate layer material film to form a semiconductor gate layer 21 of a ridge shape with the gate electrode 22 disposed at a width intermediate portion of a front surface thereof. The third step includes a first etching step for forming a first portion 22A from an upper end to a thickness direction intermediate portion of the gate electrode 22 and a second etching step being a step differing in etching condition from the first etching step and being for forming a remaining second portion 22B of the gate electrode.

A wide gap semiconductor device has: a wide gap semiconductor layer; and a metal layer 20 provided on the wide gap semiconductor layer. The metal layer 20 has a single crystal layer 21 in an interface region at an interface with the wide gap semiconductor layer. When it is assumed that a lattice constant, in an equilibrium state, of a metal constituting the metal layer 20 is L, the single crystal layer 21 in the interface region includes a first region in which a lattice constant L1 is smaller than L by 1.5% to 8%.

A wide gap semiconductor device has: a wide gap semiconductor layer; and a metal layer 20 provided on the wide gap semiconductor layer. The metal layer 20 has a single crystal layer 21 in an interface region at an interface with the wide gap semiconductor layer. When it is assumed that a lattice constant, in an equilibrium state, of a metal constituting the metal layer 20 is L, the single crystal layer 21 in the interface region includes a first region in which a lattice constant L1 is smaller than L by 1.5% to 8%.

An object of the present invention is to provide a Schottky barrier diode less liable to cause dielectric breakdown due to concentration of an electric field. A Schottky barrier diode according to this disclosure includes a semiconductor substrate made of gallium oxide, a drift layer made of gallium oxide and provided on the semiconductor substrate, an anode electrode brought into Schottky contact with the drift layer, and a cathode electrode brought into ohmic contact with the semiconductor substrate. The drift layer has an outer peripheral trench surrounding the anode electrode in a plan view. The surface of the drift layer positioned between the anode electrode and the outer peripheral trench is covered with a semiconductor layer having a conductivity type opposite to that of the drift layer.

An object of the present invention is to provide a Schottky barrier diode less liable to cause dielectric breakdown due to concentration of an electric field. A Schottky barrier diode according to this disclosure includes a semiconductor substrate made of gallium oxide, a drift layer made of gallium oxide and provided on the semiconductor substrate, an anode electrode brought into Schottky contact with the drift layer, and a cathode electrode brought into ohmic contact with the semiconductor substrate. The drift layer has an outer peripheral trench surrounding the anode electrode in a plan view. The surface of the drift layer positioned between the anode electrode and the outer peripheral trench is covered with a semiconductor layer having a conductivity type opposite to that of the drift layer.