A method for fabricating a semiconductor device includes forming a trench in a substrate, forming a gate dielectric layer on a surface of the trench, forming a lower gate, which partially fills the trench, over the gate dielectric layer, forming a low work function layer over the lower gate, forming a spacer over the low work function layer, etching the low work function layer to be self-aligned with the spacer in order to form vertical gate on both upper edges of the lower gate, and forming an upper gate over the lower gate between inner sidewalls of the vertical gate.

A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.

Systems, apparatuses, and methods may provide for technology for forming a gate polysilicon for 3D-NAND complementary metal-oxide semiconductor under array (CuA) on a substrate with a barrier and spacer structure. For example, the technology includes forming a titanium nitride (TiN) barrier adjacent the gate polysilicon and forming a silicon nitride (SiN) spacer around the polysilicon gate and the titanium nitride barrier.

A semiconductor device having an active portion and a gate pad portion on a semiconductor substrate includes: a first semiconductor layer of a first conductivity type; and a second semiconductor layer of a second conductivity type. The active portion has: first semiconductor regions of the first conductivity type; a first electrode provided on the first semiconductor regions; and first trenches. The gate pad portion has: a gate electrode pad provided above the second semiconductor layer; second trenches provided beneath the gate electrode pad; and second semiconductor regions of the second conductivity type, each provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the second trenches. Each of the second trenches is continuous with a respective one of the first trenches. The second semiconductor layer is continuous from the active portion to the gate pad portion.

Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.

Disclosed is a fin field-effect transistor having size-reduced source/drain regions so that a merging phenomenon of epitaxial structures between transistors in a layout is prevented, thus increasing the number of transistors per unit area, and so that an additional mask process is not required, thus maintain processing costs without change, and a method of manufacturing the same.

A semiconductor device includes a semiconductor substrate of a first conductivity type, having an active portion and a gate pad portion; a first semiconductor layer of the first conductivity type; and a second semiconductor layer of a second conductivity type. The active portion has first semiconductor regions of the first conductivity type, first trenches, gate insulating films, first gate electrodes, an interlayer insulating film, and second semiconductor regions of the second conductivity type. The gate pad portion has at least one second trench, an insulating film 9b, at least one second gate electrode, at least one fourth semiconductor region of the second conductivity type, and a gate electrode pad. Between the gate electrode pad and the semiconductor substrate, a polycrystalline silicon film is provided.

A semiconductor device includes a first region that contains a first conductive type impurity and is provided on a substrate, a second region that is provided in the first region and contains the first conductive type impurity at a higher concentration than the first region, a first structure that is provided on the substrate on one side of the second region in a first direction along the substrate and has a first sidewall at least on the second region side, a second structure that is provided on the substrate on the other side of the second region in the first direction and has a second sidewall at least on the second region side, and a contact that passes between the first and second sidewalls facing each other across the second region, extends to the second region, and is electrically connected to the second region.

Embodiments provide a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes: a source region and a drain region arranged at intervals on a substrate; a gate oxide layer arranged between the source region and the drain region; a gate structure arranged on the gate oxide layer; and a conductive plug arranged at a corresponding location of the source region and a corresponding location of the drain region. The gate structure includes a conductive layer having a recessed side surface facing toward the conductive plug. Compared with a traditional gate structure, in the solutions of the present disclosure, a distance between the conductive layer having the recessed side surface and the conductive plug is increased, thereby reducing a parasitic capacitance between the gate structure and the conductive plug, such that capacitances between a gate and the source/drain region are reduced, and device characteristics are improved.

The present disclosure provides a semiconductor structure and a forming method thereof, including: a gate structure is located on a substrate; a plurality of doped regions, located in the substrate, and located at two sides of the gate structure, the doped region includes a first doped region and a second doped region, a concentration of doped ions in the first doped region is greater than a concentration of doped ions in the second doped region, and the first doped region is far from a sidewall of the gate structure; an electrical contact layer, the electrical contact layer is in contact with a sidewall of the first doped region far from the gate structure, and a top surface of the electrical contact layer is higher than a surface of the substrate; and a dielectric layer, the dielectric layer fills a space between the electrical contact layer and the gate structure.