Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.

A semiconductor device includes a substrate, a 2-D material layer, source/drain contacts, and a gate electrode. The 2-D material layer is over the substrate, the 2-D material layer includes source/drain regions and a channel region between the source/drain regions, in which the 2-D material layer is made of a transition metal dichalcogenide (TMD). The source/drain contacts are in contact with source/drain regions of the 2-D material layer, in which a binding energy of transition metal atoms at the channel region of the 2-D material layer is different from a binding energy of the transition metal atoms at the source/drain regions of the 2-D material layer. The gate electrode is over the substrate.

A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns, and a gate dielectric layer between the gate electrode and the semiconductor patterns. An inner spacer of the gate dielectric layer includes a horizontal portion between the high-k dielectric layer and the second semiconductor pattern, a vertical portion between the high-k dielectric layer and the source/drain pattern, and a corner portion between the horizontal portion and the vertical portion. A first thickness of the horizontal portion is less than a second thickness of the vertical portion. The second thickness of the vertical portion is less than a third thickness of the corner portion.

Provided are a logic switching device and a method of manufacturing the same. The logic switching device may include a domain switching layer adjacent to a gate electrode. The domain switching layer may include a ferroelectric material region and an anti-ferroelectric material region. The domain switching layer may be a non-memory element. The logic switching device may include a channel, a source and a drain both connected to the channel, the gate electrode arranged to face the channel, and the domain switching layer provided between the channel and the gate electrode.

A semiconductor device is provided. The semiconductor device includes a substrate, an active pattern extending in a first direction on the substrate, a gate electrode extending in a second direction intersecting the first direction on the active pattern, a gate spacer extending in the second direction along side walls of the gate electrode, an interlayer insulating layer contacting side walls of the gate spacer, a trench formed on the gate electrode in the interlayer insulating layer, a first capping pattern provided along side walls of the trench, at least one side wall of the first capping pattern having an inclined profile, and a second capping pattern provided on the first capping pattern in the trench.

According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive layers, first and second insulating films. The electrodes are arranged in a first direction. The interlayer insulating film is provided between the electrodes. The semiconductor layer extends in the first direction in the electrodes and the interlayer insulating film. The conductive layers are provided between each of the electrodes and the semiconductor layer, and separated from each other in the first direction. The first insulating film is provided between the conductive layers and the semiconductor layer. The second insulating film is provided between each of the electrodes and the conductive layers, and extends between each of the electrodes and the interlayer insulating film adjacent to the each of the electrodes. A width of the conductive layers in the first direction is narrower than that of the second insulating film.

A device comprises a substrate, a semiconductor channel over the substrate, and a gate structure over and laterally surrounding the semiconductor channel. The gate structure comprises a first dielectric layer comprising a first dielectric material including dopants. A second dielectric layer is on the first dielectric layer, and comprises a second dielectric material substantially free of the dopants. A metal fill layer is over the second dielectric layer.

A multiple gate dielectrics and dual work-functions field effect transistor (MGO-DWF-FET) is provided on an active region of a semiconductor substrate. The MGO-DWF-FET includes a first functional gate structure including a U-shaped first high-k gate dielectric material layer and a first work-function metal-containing structure, and a laterally adjacent, and contacting, second functional gate structure that includes a U-shaped second high-k gate dielectric material layer and a second work-function metal-containing structure. The first functional gate structure has a gate length that differs from a gate length of the second functional gate structure.

Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.

According to one embodiment, a semiconductor device includes first to third electrodes, a semiconductor member, and a first insulating member. The third electrode is between the first and second electrodes. The semiconductor member includes first and second semiconductor regions. The first semiconductor region includes first to fifth partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial regions. The second semiconductor region includes first and second semiconductor portions. The first insulating member includes first to third insulating regions. The fourth partial region includes a first facing region. The fifth partial region includes a second facing region. The first facing region includes a first element. The second facing region does not include the first element, or a concentration of the first element in the second facing region is lower than in the first facing region.