A high-voltage fast-avalanche diode, being a silicon-avalanche shaper or sharpener (SAS), has a thick active region above 300 microns in thickness.

A semiconductor device including an interconnect. The interconnect is arranged to transfer current from one terminal to another, and the interconnect includes a first layer including a plurality of interweaved fingers, and each of the interweaved fingers varies in width in a direction of propagation current thereby resulting in a difference of resistance within each of the interweaved fingers in the direction of propagation of current; a second layer arranged below the first layer. The second layer compensates for the difference of resistance in the first layer.

A protection device includes a first inductive element connecting first and second terminals and a second inductive element connecting third and fourth terminals. A first component includes a first avalanche diode connected in parallel with a first diode string, anodes of the first avalanche diode and a last diode in the string being connected to ground, cathodes of the first avalanche diode and a first diode in the string being connected, and a tap of the first diode string being connected to the first terminal. A second protection component includes a second avalanche diode connected in parallel with a second diode string, anodes of the second avalanche diode and a last diode in the string being connected to ground, cathodes of the second avalanche diode and a first diode in the string being connected, and a tap of the second diode string being connected to the third terminal.

A method for fabricating a low-gain avalanche diode (LGAD) device is provided. The method includes: forming a low-resistivity n-type semiconductor substrate in a first silicon wafer; forming a p-type gain layer in an upper surface of a high-resistivity p-type second silicon wafer; bonding the first and second wafers such that the upper surface of the second wafer proximate the gain layer contacts the semiconductor substrate in the first wafer to form a bonded wafer structure, whereby a back surface of the second wafer becomes an upper surface of the bonded wafer structure; forming a plurality of p-type electrodes in the upper surface of the bonded wafer structure; and forming a conductive layer on at least a portion of the respective p-type electrodes and on a back surface of the semiconductor substrate, the conductive layer providing electrical connection to the LGAD device.

An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V−).

An integrated circuit includes a shallow P-type well (SPW) below a surface of a semiconductor substrate and a shallow N-type well (SNW) below the surface. The SPW forms an anode of a diode and the SNW forms a cathode of the diode. The SNW is spaced apart from the SPW by a well space region; and a thin field relief oxide structure lies over the well space region.

A semiconductor device includes a semiconductor substrate of a first conductivity type, having a first principal surface and a second principal surface, a silicon carbide semiconductor layer of the first conductivity type, disposed on the first principal surface, a first electrode disposed on the silicon carbide semiconductor layer, and a second electrode disposed on the second principal surface and forming an ohmic junction with the semiconductor substrate. The semiconductor device satisfies 0.13≦Rc/Rd, where Rc is the contact resistance between the second principal surface and the second electrode at room temperature and Rd is the resistance of the silicon carbide semiconductor layer in a direction normal to the first principal surface at room temperature.

A method of forming a semiconductor device may include providing a semiconductor substrate, the semiconductor substrate comprising an inner region of a first polarity, and a surface layer, disposed on the inner region, wherein the surface layer comprises a second polarity, opposite the first polarity. The method may further include removing a surface portion of the semiconductor substrate using a saw, wherein a trench region is formed within the semiconductor substrate, and cleaning the trench region using a chemical process, wherein at least one mesa structure is formed within the semiconductor substrate.

The invention relates to an avalanche diode that can be employed as an ESD protection device. An avalanche ignition region is formed at the p-n junction of the diode and includes an enhanced defect concentration level to provide rapid onset of avalanche current. The avalanche ignition region is preferably formed wider than the diode depletion zone, and is preferably created by placement, preferably by ion implantation, of an atomic specie different from that of the principal device structure. The doping concentration of the placed atomic specie should be sufficiently high to ensure substantially immediate onset of avalanche current when the diode breakdown voltage is exceeded. The new atomic specie preferably comprises argon or nitrogen, but other atomic species can be employed. However, other means of increasing a defect concentration level in the diode depletion zone, such as an altered annealing program, are also contemplated.

An electronic component includes first and second separate semiconductor regions. A third semiconductor region is arranged under and between the first and second semiconductor regions. The first and third semiconductor regions define electrodes of a first diode. The second and third semiconductor regions define electrodes of a second diode. The first diode is an avalanche diode.