A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

We herein describe a method of manufacturing a semiconductor device having one or more trenches with an insulation layer. The one or more trenches with an insulation layer are manufactured using the steps of performing an etching process to form the one or more trenches, forming a first insulation layer on a lower surface and sidewalls of the one or more trenches, depositing a hydrophilic layer over the first insulation layer, depositing a photoresist material in the one or more trenches, wherein depositing a photoresist material comprises exposing the hydrophilic layer on an upper region of a first side of the one or more trenches, performing a wet etch process to etch the insulation layer on the sidewall of the first side of the one or more trenches to a predetermined distance below a surface of the photoresist material, removing the photoresist material, removing the hydrophilic layer, and after performing the wet etch process, removing the photoresist material, and removing the hydrophilic layer, and forming a second insulation layer on the sidewall of the first side of the one or more trenches.

The present invention discloses a vertical semiconductor device and a manufacturing method thereof. The vertical semiconductor device includes: a substrate having a first surface and a second surface, the substrate including a conductive array formed by multiple conductive plugs through the substrate; a semiconductor layer formed on the first surface, the semiconductor layer having a third surface and a fourth surface, wherein the fourth surface faces the first surface; a first electrode formed on the third surface; and a second electrode formed on the second surface for electrically connecting to the conductive array.

A semiconductor device includes a substrate, a drift layer provided on an upper surface side of the substrate, a base layer provided on the upper surface side of the drift layer, an upper semiconductor layer provided on the upper surface side of the base layer, a first electrode provided on the upper surface of the substrate, a second electrode provided on a rear surface of the substrate, a trench extending to the drift layer from the upper surface of the substrate and a gate electrode provided inside the trench, wherein an inner side surface of the trench has a first surface and a second surface provided below the first surface, the second surface tilts inward of the trench with respect to the first surface, and an intersection point of the first surface and the second surface is provided below the base layer.

A lateral bipolar transistor includes an emitter region doped with a first conductivity type, having a first width and a first average doping concentration; a collector region doped with the first conductivity type, having a second width greater than the first width of the emitter region and a second average doping concentration lower than the first average doping concentration ; and a base region positioned between the emitter and collector regions. The emitter, collector and base regions are arranged in a silicon layer on an insulator layer on a substrate. A substrate region that is deprived of the silicon and insulator layers is positioned on a side of the collector region. A bias circuit is coupled, and configured to deliver, to the substrate region a bias voltage. This bias voltage is controlled to modulate an electrostatic doping of the collector region.

A semiconductor device includes a substrate, a drift layer provided on an upper surface side of the substrate, a base layer provided on the upper surface side of the drift layer, an upper semiconductor layer provided on the upper surface side of the base layer, a first electrode provided on the upper surface of the substrate, a second electrode provided on a rear surface of the substrate, a trench extending to the drift layer from the upper surface of the substrate and a gate electrode provided inside the trench, wherein an inner side surface of the trench has a first surface and a second surface provided below the first surface, the second surface tilts inward of the trench with respect to the first surface, and an intersection point of the first surface and the second surface is provided below the base layer.

The present disclosure provides a semiconductor structure and a manufacturing method thereof. In the manufacturing method, a first P-type semiconductor layer is provided, and an N-type semiconductor layer and a second P-type semiconductor layer are formed in sequence on the first P-type semiconductor layer. The first P-type semiconductor layer, the N-type semiconductor layer and the second P-type semiconductor layer all include a GaN-based material. When the first P-type semiconductor layer is provided, its upper surface is controlled to be a Ga surface; when the N-type semiconductor layer is formed, its upper surface is controlled to be an N surface; when the second P-type semiconductor layer is formed, its upper surface is controlled to be an N surface. By use of the directivity of wet etching, etching is started from the N surface of the second P-type semiconductor layer and automatically stopped on the Ga surface of the first P-type semiconductor layer 12, thereby avoiding over-etching of the first P-type semiconductor layer and decreased hole carrier concentration. Afterwards, dry etching is performed on the second P-type semiconductor layer and stopped on the upper surface of the N-type semiconductor layer, thus helping to reduce a contact resistance of an electrical connection structure of the N-type semiconductor layer.

A logic gate cell structure is disclosed. The logic gate cell structure includes a substrate, a channel layer disposed over the substrate, and a field-effect transistor (FET) contact layer disposed over the channel layer. The FET contact layer is divided by an isolation region into a single contact region and a combined contact region. The channel layer and the FET contact layer form part of a FET device. A collector layer is disposed within the combined contact region over the FET contact layer to provide a current path between the channel layer and the collector layer though the FET contact layer. The collector layer, a base layer, and an emitter layer form part of a bipolar junction transistor.

A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.