The present invention discloses a method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz: sequentially growing, on a silicon substrate, an N-polar GaN buffer layer, a carbon doped semi-insulated N-polar GaN layer, a non-doped N-polar AlGaN layer, a non-doped N-polar GaN layer and a non-doped N-polar InGaN thin film to obtain a rectifier epitaxial wafer; preparing a pattern groove for a schottky contact electrode on the GaN rectifier epitaxial wafer, and depositing the schottky contact electrode in the groove; preparing a pattern for an ohmic contact electrode, and depositing a device ohmic contact electrode on the surface of the epitaxial wafer; subsequently, depositing a silicon nitride passivation layer at a part where there is no electrode on the surface of the epitaxial wafer, and preparing a surface electrode area; and finally, performing mesa isolation treatment on the GaN rectifier epitaxial wafer. The present invention realizes the preparation of a high-frequency GaN rectifier, and improves the performance stability of a rectifier device operating at a high power.

A high-frequency conductor having improved conductivity comprises at least one electrically conductive base material. The ratio of the outer and inner surfaces of the base material permeable by a current to the total volume of the base material is increased by a) dividing the base material perpendicularly to the direction of current into at least two segments, which are spaced from each other by an electrically conductive intermediate piece and connected both electrically and mechanically to each other, and/or b) topographical structures in or on the surface of the base material and/or c) inner porosity of at least a portion of the base material compared to a design of the base material in which the respective feature was omitted. It was found that, as a result of these measures concerning the design, it is possible to physically arrange the same amount abase material so that a larger fraction of the base material is located at a distance of no more than skin depth from an outer or inner surface and is thus involved in current transport. As a result, a lesser fraction remains unused as a function of the skin effect.

According to an embodiment of the present invention, a method of manufacturing a FET device having a set BTBT leakage and a maximum V.sub.DD includes: determining an x value in In.sub.xGa.sub.1−xAs according to the BTBT leakage and the maximum V.sub.DD, and forming a channel utilizing In.sub.xGa.sub.1−xA, wherein x is not 0.53.

Because of inclusion of: a source electrode that is formed on a front surface of a semiconductor substrate and that is joined to the semiconductor substrate both at a source electrode as a first contact region that is an ohmic contact region and at a source electrode as a second contact region that is a contact region with a non-ohmic contact or the like; a back-surface electrode formed on a back surface of the semiconductor substrate; and a through hole in which an interconnection is provided that connects the source electrode as the second contact region in the source electrode with the back-surface electrode; it is possible not only to improve the corrosion resistance but also to reduce the leakage current, so that a highly-reliable semiconductor device suited for high frequency operation is provided.

A method for manufacturing a semiconductor device, includes forming source and drain electrodes on a semiconductor layer provided above a substrate; forming a first insulating film covering a surface of the semiconductor layer, between the source and drain electrodes, forming a second insulating film on the first insulating film, forming a mask on the second insulating film, the mask having an opening between the source and drain electrodes in a plan view viewed in a direction perpendicular to a substrate surface, forming a first gate opening in the first insulating film and forming a second gate opening in the second insulating film, by etching the first and second insulating films through the opening, and forming a gate electrode on the first and second insulating films, the gate electrode making a Schottky contact with the semiconductor layer through the first and second gate openings.

Because of inclusion of: a source electrode that is formed on a front surface of a semiconductor substrate and that is joined to the semiconductor substrate both at a source electrode as a first contact region that is an ohmic contact region and at a source electrode as a second contact region that is a contact region with a non-ohmic contact or the like; a back-surface electrode formed on a back surface of the semiconductor substrate; and a through hole in which an interconnection is provided that connects the source electrode as the second contact region in the source electrode with the back-surface electrode; it is possible not only to improve the corrosion resistance but also to reduce the leakage current, so that a highly-reliable semiconductor device suited for high frequency operation is provided.

The present invention discloses a method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz: sequentially growing, on a silicon substrate, an N-polar GaN buffer layer, a carbon doped semi-insulated N-polar GaN layer, a non-doped N-polar AlGaN layer, a non-doped N-polar GaN layer and a non-doped N-polar InGaN thin film to obtain a rectifier epitaxial wafer; preparing a pattern groove for a schottky contact electrode on the GaN rectifier epitaxial wafer, and depositing the schottky contact electrode in the groove; preparing a pattern for an ohmic contact electrode, and depositing a device ohmic contact electrode on the surface of the epitaxial wafer; subsequently, depositing a silicon nitride passivation layer at a part where there is no electrode on the surface of the epitaxial wafer, and preparing a surface electrode area; and finally, performing mesa isolation treatment on the GaN rectifier epitaxial wafer. The present invention realizes the preparation of a high-frequency GaN rectifier, and improves the performance stability of a rectifier device operating at a high power.

A semiconductor device is provided. The semiconductor device includes a substrate; an active layer disposed on the substrate; a via through the active layer; and a plurality of electrodes disposed on the active layer and into the via. Additionally, a package structure that includes the semiconductor device is also provided. The electrode is electrically connected to the substrate through the via.

A semiconductor structure includes: a first semiconductor layer, including a first surfaces and a second surfaces opposite to the first surface; a second semiconductor layer, disposed on the first semiconductor layer, where a conductive type of the second semiconductor layer is the same as that of the first semiconductor layer, and a doping concentration of the second semiconductor layer is less than that of the first semiconductor layer; grooves, formed in the second semiconductor layer; and a third semiconductor layer, where a conductive type of the third semiconductor layer is different from that of the second semiconductor layer, a material of the third semiconductor layer is different from that of the second semiconductor layer, and at least a portion of the third semiconductor layer is disposed in the grooves.

A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.