A reverse conducting power semiconductor device includes a plurality of thyristor cells and a freewheeling diode are integrated in a semiconductor wafer. The freewheeling diode includes a diode anode layer, a diode anode electrode, a diode cathode layer, and a diode cathode electrode. The diode cathode layer includes diode cathode layer segments, each of which is stripe-shaped and arranged within a corresponding stripe-shaped first diode anode layer segment such that a longitudinal main axis of each diode cathode layer segment extends along the longitudinal main axis of the corresponding one of the first diode anode layer segments.

Aspects of the present disclosure include one or more semiconductor electrostatic discharge protection devices. At least one embodiment includes a semiconductor electrostatic discharge device with one or more fingers divided into two segments with alternating p-diffusion and n-diffusion regions, with each region being associated with at least one of a portion of a diode and/or silicon-controlled rectifier (SCR).

After the various regions of a vertical power device are formed in or on the top surface of an n-type wafer, the wafer is thinned, such as by grinding. A drift layer may be n-type, and various n-type regions and p-type regions in the top surface contact a top metal electrode. A blanket dopant implant through the bottom surface of the thinned wafer is performed to form an n− buffer layer and a bottom p+ emitter layer. Energetic particles are injected through the bottom surface to intentionally damage the crystalline structure. A wet etch is performed, which etches the damaged crystal at a much greater rate, so some areas of the n− buffer layer are exposed. The bottom surface is metallized. The areas where the metal contacts the n− buffer layer form cathodes of an anti-parallel diode for conducting reverse voltages, such as voltage spikes from inductive loads.

A power semiconductor device includes a semiconductor wafer, a thyristor structure, and a bipolar junction transistor. The thyristor structure includes a first emitter layer of a first conductivity type adjacent the first main side, a first base layer of a second conductivity type, a second base layer of the first conductivity type, a second emitter layer of the second conductivity type, a gate electrode, a first main electrode, and a second main electrode arranged. The bipolar junction transistor includes a base electrode electrically separated from the gate electrode, a third main electrode arranged on the first main side and a fourth main electrode arranged on the second main side. The first main electrode is electrically connected to the third main electrode and the second main electrode is electrically connected to the fourth main electrode.

A turn-off power semiconductor device includes first and second thyristor cells, a common gate contact and a plurality of stripe-shaped electrically conductive first gate runners. Each first gate runner has a first end portion, a second end portion opposite to the first end portion and a first connecting portion connecting the first end portion and the second end portion. The first end portion is directly connected to the common gate contact. The first gate electrode layer portions of all first thyristor cells are implemented as a first gate electrode layer. The second gate electrode layer portions of all second thyristor cells are implemented as a second gate electrode layer. The first gate electrode layer is directly connected to the common gate contact. At least the first connecting portion of each first gate runner is separated from the first gate electrode layer.

B-TRAN bipolar power transistor devices and methods, using a drift region which is much thinner than previously proposed double-base bipolar transistors of comparable voltage. This is implemented in a high-bandgap semiconductor material (preferably silicon carbide). Very high breakdown voltage, and fast turn-off, are achieved with very small on-resistance.

A triac has a vertical structure formed from a silicon substrate having an upper surface side. A main metallization on the upper surface side has a first portion resting on a first region of a first conductivity type formed in a layer of a second conductivity type. A second portion of the main metallization rests on a portion of the layer. A gate metallization on the upper surface side rests on a second region of the first conductivity type formed in the layer in the vicinity of the first region. A porous silicon bar formed in the layer at the upper surface side has a first end in contact with the gate metallization and a second end in contact with the main metallization.

An apparatus includes: a first SCR device having a first source terminal coupled to a signal terminal, a first body terminal coupled to the first source terminal, a first gate terminal coupled to the signal terminal, and a first drain terminal; a second SCR device having a second drain terminal coupled to the first drain terminal, a second gate terminal coupled to a reference voltage terminal; and a second source terminal coupled to the reference voltage terminal. The apparatus also includes: a third SCR device having a third source terminal coupled to the signal terminal, a third gate terminal coupled to the first gate terminal, and a third drain terminal; a first capacitor coupled between the third drain terminal and the second gate terminal; and a second capacitor coupled between the second gate terminal and the reference voltage terminal.

A hybrid semiconductor bipolar switch in which a normally-on high-voltage wide-bandgap semiconductor bipolar switch and a normally-off field effect transistor are connected in a cascode (Baliga-pair) configuration. The switch may be constructed as a stacked hybrid device where a discrete transistor is bonded on top of a bipolar switch. Power systems may use plural switches paired with anti-parallel diodes.

An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection layer.