A quantum dot device is disclosed that includes a quantum well stack, a first and a second plunger gates above the quantum well stack, and a passive barrier element provided in a portion of the quantum well stack between the first and the second plunger gates. The passive barrier element may serve as means for localizing charge in the quantum dot device and may be used to replace charge localization control by means of a barrier gate. In general, a quantum dot device with a plurality of plunger gates provided over a given quantum well stack may include a respective passive barrier element between any, or all, of adjacent plunger gates in the manner as described for the first and second plunger gates.

A quantum processing system is disclosed. In one embodiment, a quantum processing system comprises: a plurality of donor atoms positioned in a silicon crystal substrate, each donor atom positioned at a donor site; and a plurality of conductive control electrodes arranged about the donor atoms to operate the donor atoms as qubits. Where, at least two pairs of nearest neighbour donor atoms of the plurality of donor atoms are arranged along the [110] direction of the silicon crystal substrate and are configured to operate as qubits.

Methods, devices, and systems are described for storing and transferring quantum information. An example device may comprise at least one semiconducting layer, one or more conducting layers configured to define at least two quantum states in the at least one semiconducting layer and confine an electron in or more of the at least two quantum states, and a magnetic field source configured to generate an inhomogeneous magnetic field. The inhomogeneous magnetic field may cause a first coupling of an electric charge state of the electron and a spin state of the electron. The device may comprise a resonator configured to confine a photon. An electric-dipole interaction may cause a second coupling of an electric charge state of the electron to an electric field of the photon.

A novel and useful modified semiconductor fabrication technique for realizing reliable semiconductor quantum structures. Quantum structures require a minimization of the parasitic capacitance of the control gate and the quantum well. The modified semiconductor process eliminates the fabrication of the metal, contact, and optionally the raised diffusion layers from the quantum wells, thereby resulting in much lower well and gate capacitances and therefore larger Coulomb blockade voltages. This allows easier implementation of the electronic control circuits in that they can have larger intrinsic noise and relaxed analog resolution. Several processes are disclosed including implementations of semiconductor quantum structures with tunneling through an oxide layer as well as tunneling through a local well depleted region. These techniques can be used in both planar semiconductor processes and 3D, e.g., FinFET, semiconductor processes. A dedicated process masking step is used for realizing the raised diffusions. In addition, the edge of the raised diffusion layer may be placed either in the gate region or the active layer region.

Processor elements are described herein. A processor element comprises a silicon layer. The processor element further comprises one or more conductive electrodes. The processor element further comprises dielectric material having a non-uniform thickness, the dielectric material disposed at least between the silicon layer and the one or more conductive electrodes. In use, when a bias potential is applied to one or more of the conductive electrodes, the positioning of the one or more conductive electrodes and the non-uniform thickness of the dielectric material together define an electric field profile to induce a quantum dot at an interface between the silicon layer and the dielectric layer. Methods are also described herein.

Disclosed are a functional photoresist for patterning a nanoparticle thin film including nanoparticles on a substate and a method of patterning a nanoparticle thin film using the functional photoresist, wherein the functional photoresist includes a photoactive compound (PAC); and a functional ligand that is bound to the surfaces of the nanoparticles and controls the physical properties of the nanoparticles.

A method for the patterning and control of single electrons on a surface is provided that includes implementing scanning tunneling microscopy hydrogen lithography with a scanning probe microscope to form charge structures with one or more confined charges; performing a series of field-free atomic force microscopy measurements on the charge structures with different tip heights, where interaction between the tip and the confined charge are elucidated; and adjusting tip heights to controllably position charges within the structures to write a given charge state. The present disclose also provides a Gibb's distribution machine formed with the method for the patterning and control of single electrons on a surface. A multi bit true random number generator and neural network learning hardware formed with the above described method are also provided.

A method for processing a semiconductor device with two closely space gates comprises forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is formed by the removed sub-structure.

A semiconductor device made on a substrate including an active region and a non-active region at least partially surrounding the active region, a plurality of gate stacks, a part of each gate stack being on the active region, each gate stack being separated from adjacent gate stacks by a spacer by a distance e, the device being such that, for each gate stack, the part of the gate stack located on the active region has a height h.sub.2, the part of the same gate stack located on the non-active region has a height h.sub.1, and h.sub.2/e=a.sub.2 and h.sub.1/e=a.sub.1<a.sub.lim where a.sub.2 is an aspect ratio such that, upon growth of the spacer material forming the spacers, an airgap is in the spacer, and a.sub.1 is an aspect ratio such that, upon growth of the spacer material forming the spacers, no airgap is in the spacer.

An electronic component (10) is formed by a semiconductor component or a semiconductor-like structure having gate electrode assemblies (16, 18), for reading out the quantum state of a qubit in a quantum dot (42). The electronic component (10) comprises a substrate (12) having a two-dimensional electron gas or electron hole gas. Electrical contacts connect the gate electrode assemblies (16, 18) to voltage sources. The gate electrode assemblies (16, 18) have gate electrodes (20, 22, 30, 32, 34, 38, 40), which are arranged on a surface (14) of the electronic component (10), for producing potential wells (46, 48, 62, 64, 66) in the substrate (12).