A high voltage device is used as a lower switch in a power stage of a switching regulator. The high voltage device includes at least one lateral diffused metal oxide semiconductor (LDMOS) device, a first isolation region, a second isolation region, a third isolation region, and a current limiting device. The first isolation region is located in a semiconductor layer, and encloses the LDMOS device. The second isolation region has a first conductivity type, and encloses the first isolation region in the semiconductor layer. The third isolation region has a second conductivity type, and encloses the second isolation region in the semiconductor layer. The current limiting device is electrically connected to the second isolation region, and is configured to operably suppress a parasitic silicon controlled rectifier (SCR) from being turned on.

A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region.

Described examples include an integrated circuit having a semiconductor substrate having an epitaxial layer located thereon, the epitaxial layer having a surface. The integrated circuit also has a buried layer formed in the semiconductor substrate, the epitaxial layer located between the buried layer and the surface. The integrated circuit also has a Schottky contact and an ohmic contact formed on the surface. The integrated circuit also has a Pdrift region in the epitaxial layer located between the ohmic contact and the Schottky contact.

A high voltage device for use as an up-side switch of a power stage circuit includes: at least one lateral diffused metal oxide semiconductor (LDMOS) device, a second conductivity type isolation region and at least one Schottky barrier diode (SBD). The LDMOS device includes: a well formed in a semiconductor layer, a body region, a gate, a source and a drain. The second conductivity type isolation region is formed in the semiconductor layer and is electrically connected to the body region. The SBD includes: a Schottky metal layer formed on the semiconductor layer and a Schottky semiconductor layer formed in the semiconductor layer. The Schottky semiconductor layer and the Schottky metal layer form a Schottky contact. In the semiconductor layer, the Schottky semiconductor layer is adjacent to and in contact with the second conductivity type isolation region.

Described examples include an integrated circuit having a semiconductor substrate having an epitaxial layer located thereon, the epitaxial layer having a surface. The integrated circuit also has a buried layer formed in the semiconductor substrate, the epitaxial layer located between the buried layer and the surface. The integrated circuit also has a Schottky contact and an ohmic contact formed on the surface. The integrated circuit also has a Pdrift region in the epitaxial layer located between the ohmic contact and the Schottky contact.

A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region.

A power transistor having: a p-body region, coupled to a first voltage; a first p-type buried layer under the p-body region; a n-implant region surrounding the p-body region and the p-type buried layer; a p-implant region surrounding the n-implant region; and a p-implant guard ring region inserted into the n-implant region to split the n-implant region to a first part and a second part, wherein the first part of the n-implant region is between the p-body region and the p-implant guard ring region, and the second part of the n-implant region is between the p-implant guard ring region and the p-implant region; wherein the second part of the n-implant region has a Schottky contact region coupled to a second voltage via a metal contact.

A high voltage device for use as a lower switch in a power stage of a switching regulator includes at least one lateral diffused metal oxide semiconductor (LDMOS) device and at least one Schottky barrier diode (SBD). The LDMOS device includes: a well, a body region, a gate, a source, and a drain. The SBD includes a Schottky metal layer and a Schottky semiconductor layer. The Schottky metal layer is electrically connected to the source, and the Schottky semiconductor layer is in contact with the well.

A multi-level gate driver applied to the SiC metal-oxide-semiconductor field-effect transistor (MOSFET) includes three parts: the SiC MOSFET information detection circuit, the signal level shifting circuit, and the segmented driving circuit. The SiC MOSFET information detection circuit includes the SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit. The segmented driving circuit includes a turn-on segmented driving circuit and a turn-off segmented driving circuit. The SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit process a drain-source voltage and a drain-source current during the SiC MOSFET's switching as enable signals for segmented driving; the signal level shifting circuit transfers enable signals required by the segmented driving circuit to the suitable power supply rail; and the SiC MOSFET turn-on segmented driving circuit and the turn-off segmented driving circuit select suitable driving currents.

A lateral transistor having a well region, a body region, a source region, a drain region, a gate structure and a trenched Schottky barrier structure. The trenched Schottky barrier structure extended vertically from a top surface of the well region through the source region and the body region and penetrated into at least a portion of the well region to form a vertical Schottky contact.