A semiconductor device includes: a substrate (10); a semiconductor layer (20) disposed on a main surface of this substrate (10); and a first main electrode (30) and a second main electrode (40), which are disposed on the substrate (10) separately from each other with the semiconductor layer (20) sandwiched therebetween and are individually end portions of a current path of a main current flowing in an on-state. The semiconductor layer (20) includes: a first conductivity-type drift region (21) through which a main current flows; a second conductivity-type column region (22) that is disposed inside the drift region (21) and extends in parallel to a current path; and an electric field relaxation region (23) that is disposed in at least a part between the drift region (21) and the column region (22) and is either a low-concentration region in which an impurity concentration is lower than in the same conductivity-type adjacent region or a non-doped region.

A semiconductor structure includes a substrate, an isolation layer, a dielectric layer, an insulation layer, a conductor and a capping layer. The substrate has a concave portion. The isolation layer is located on a top surface of the substrate. The dielectric layer is located on the isolation layer. The insulation layer is located on a surface of the concave portion and extends to a sidewall of the isolation layer. The conductor is located on the insulation layer in the concave portion. The conductor has a first top surface and a second top surface, and the first top surface is closer to the dielectric layer than the second top surface. The capping layer is located in the concave portion and covers the conductor.

A lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), including: a trench gate including a lower part inside a trench and an upper part outside the trench, a length of the lower part in a width direction of a conducting channel being less than that of the upper part, and the lower part extending into a body region and having a depth less than that of the body region; an insulation structure arranged between a drain region and the trench gate and extending downwards into a drift region, a depth of the insulation structure being less than that of the drift region.

A silicon chip package structure, in particular a metal-oxide-semiconductor field-effect transistor (MOSFET) and method of manufacture is provided. The disclosure provides improvements to a Chip Silicon Package (CSP) structure by reducing the active area needed to be sacrificed to create a drain area.

Disclosed are a semiconductor structure and method of forming the structure. The semiconductor structure includes an extended drain metal oxide semiconductor field effect transistor (EDMOSFET). The EDMOSFET includes, in the semiconductor layer, a body well, which has a source region therein, and a drain drift well, which abuts the body well and has a drain region therein. A trench gate structure is within the drain drift well positioned laterally between the body-drain drift junction and an internal shallow trench isolation (STI) region and the internal STI region is between the trench gate structure and the drain region. A primary gate structure is on the top surface of the semiconductor layer traversing the body-drain drift junction and optionally extending over the trench gate structure. Gate dielectric material physically separates gate conductor materials of the primary and trench gate structures. Optionally, the EDMOSFET includes more than one trench gate structure.

A lateral double-diffused metal-oxide-semiconductor transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate include a (a) gate conductor extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure and (b) a gate dielectric layer including a least three dielectric sections. Each of the at least three dielectric sections separates the gate conductor from the silicon semiconductor structure by a respective separation distance, where each of the respective separation distances is different from each other of the respective separation distances.

A method for forming a semiconductor structure includes providing a substrate, including a first region and a second region; forming a plurality of fin structures on the substrate; forming an isolation structure between adjacent fin structures; forming a mask layer over the substrate and the plurality of fin structures; forming an opening by removing a portion of the mask layer formed in the first region; removing a portion of the isolation structure exposed in the opening by using a remaining portion of the mask layer as a mask; removing the remaining portion of the mask layer; and forming a gate structure across the plurality of fin structures. The gate structure covers the first region.

A transistor includes a trench formed in a semiconductor substrate. A conductive spacer is formed in the trench and offset from a first sidewall of the trench. A dielectric material is formed in the trench and surrounds the conductive spacer. A drift region is formed in the semiconductor substrate adjacent to the first sidewall and a first portion of a second sidewall of the trench. A drain region is formed in the drift region adjacent to a second portion of the second sidewall. A first gate region overlaps a portion of the drift region and is formed separate from the conductive spacer.

An MOSFET manufacturing method, comprising: etching an oxide layer and a silicon nitride layer on a first conductivity type well region, and forming an opening exposing the first conductivity type well region; etching the first conductivity type well region to form a first trench; depositing a medium oxide layer and performing back etching; etching the first conductivity type well region to form a second trench that is connected to the first trench, and forming a grid on an inner wall of the second trench, forming a second conductivity type well region in the first conductivity type well region at the bottom of the second trench, and forming a source in the second conductivity type well region; and removing the oxide layer and the silicon nitride layer, and forming a drain at the first conductivity type well region outside of the trench.

A semiconductor structure includes a substrate, including a first region, a second region, and a third region between the first region and the second region; a first fin structure including first nanowires disposed over the first region; a second fin structure including second nanowires disposed over the second region; and a first doped layer, disposed over the third region and in contact with each first nanowire and each second nanowire. The first and second nanowires are respectively arranged along a direction perpendicular to the surface of the substrate and both contain first doping ions. The first doped layer contains second doping ions with a type opposite to the type of the first doping ions. The semiconductor structure includes a source doped layer over the first region; a drain doped layer over the second region; and a first gate structure, disposed across the first fin structure and surrounding each first nanowire.