A method for forming spacers of a gate of a field effect transistor is provided, the gate including sides and a top and being located above a layer of a semiconductor material, the method including a step of forming a dielectric layer that covers the gate; after the step of forming the dielectric layer, at least one step of modifying the dielectric layer by ion implantation while retaining non-modified portions of the dielectric layer covering sides of the gate and being at least non-modified over their entire thickness; the ions having a hydrogen base and/or a helium base; at least one step of removing the modified dielectric layer using a selective etching of the dielectric layer, wherein the removing includes a wet etching with a base of a solution including hydrofluoric acid diluted to x % by weight, with x≦0.2, and having a pH less than or equal to 1.5.

A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.

The invention relates to a deep depletion MIS transistor (100), comprising: a source region (S) and a drain region (D) made of doped semiconductor diamond of a first conductivity type; a channel region (C) made of doped semiconductor diamond of the first conductivity type, arranged between the source region and the drain region; a drift region (DR) made of doped semiconductor diamond of the first conductivity type, arranged between the channel region and the drain region; and a conductive gate (111) arranged on the channel region and separated from the channel region by a dielectric layer (113).

According to example embodiments, an integrated circuit includes a continuous active region extending in a first direction, a tie gate electrode extending in a second direction crossing the first direction on the continuous active region, a source/drain region provided adjacent the tie gate electrode, a tie gate contact extending in a third direction perpendicular to the first direction and the second direction on the continuous active region and connected to the tie gate electrode, a source/drain contact extending in the third direction and connected to the source/drain region, and a wiring pattern connected to each of the tie gate contact and the source/drain contact and extending in a horizontal direction. A positive supply power is applied to the wiring pattern.

A method for forming a transistor structure includes steps as follows: A substrate with an original surface is prepared. Next a gate conductive region is formed, wherein at least a portion of the gate conductive region is disposed below the original surface, and a bottom wall and sidewalls of the gate conductive region is surrounded by a gate dielectric layer. Then, a first conductive region is formed, wherein a bottom wall of the first conductive region is aligned or substantially aligned with a top wall of the gate conductive region.

Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

A temperature sensor integrated in a transistor array, e.g., metal-oxide-semiconductor field-effect transistor (MOSFET) array, is provided. The integrated temperature sensor may include a doped well region formed in a substrate (e.g., SiC substrate), a resistor gate formed over the doped well region, first and second sensor terminals conductively coupled to the doped well region on opposite sides of the resistor gate. The integrated temperature sensor includes a gate driver to apply a voltage to the resistor gate that affects a resistance of the doped well region below the resistor gate, and temperature analysis circuitry to determine a resistance of a conductive path passing through the doped well region, and determine a temperature associated with the transistor array.

A semiconductor device includes a substrate, a gate structure, a source region, a drain region, a doped region, and a channel region. The gate structure is disposed in the substrate, and the source region and drain regions being a first conductivity type respectively disposed at two sides of the gate structure. The doped region being a second conductivity type different from the first conductivity type is disposed below and separated from the gate structure, the source region, and drain region, the doped region. The channel region is disposed between the doped region and the gate structure and in contact with the doped region, and a dopant concentration of the channel region is less than a dopant concentration of the doped region.

In a semiconductor device according to an embodiment, a thickness of a semiconductor layer of an SOI substrate on which a field effect transistor constituting an analog circuit is formed is set to 2 nm or more and 24 nm or less.

Provided is a semiconductor device, including at least: a semiconductor layer; and a gate electrode that is arranged directly or via another layer on the semiconductor layer, the semiconductor device being configured in such a manner as to cause a current to flow in the semiconductor layer at least in a first direction that is along with an interface between the semiconductor layer and the gate electrode, the semiconductor layer having a corundum structure, a direction of an m-axis in the semiconductor layer being the first direction.