Transistors having reduced parasitics and enhanced performance. In some embodiments, a transistor can include a source and a drain each implemented as a first type active region, and a gate implemented relative to the source and the drain such that application of a voltage to the gate results in formation of a conductive channel between the source and the drain. The transistor can further include a body configured to provide the conductive channel upon the application of the voltage to the gate. The body can be implemented as a second type active region that butts with the first type active region on the source side at a respective area not covered by the gate, and does not butt with the first type active region on the drain side at a respective area not covered by the gate.

A display device and a method of manufacturing a display device are provided. A display device includes a lower conductive pattern disposed on a substrate, a lower insulating layer disposed on the lower conductive pattern, the lower insulating layer including a first lower insulating pattern including an overlapping region overlapping the lower conductive pattern, and a protruding region. The display device includes a semiconductor pattern disposed on the first lower insulating pattern and having a side surface, the side surface being aligned with a side surface of the first lower insulating pattern or disposed inward from the side surface of the first lower insulating pattern, a gate insulating layer disposed on the semiconductor pattern, a gate electrode disposed on the gate insulating layer, and an empty space disposed between the substrate and the protruding region of the first lower insulating pattern.

A field-effect transistor (FET) and a radio-frequency module are provided comprising an active region comprising a source region, a drain region, a body region disposed between the source region and the drain region, a first body extension portion in contact with the body region, a second body extension portion in contact with the body region, and a body contact region in contact with the first extension portion and the second extension portion; and a gate disposed on a top surface of the body region. A die is also provided comprising two or more such FETs.

A metal oxide semiconductor field effect transistor preferably fabricated with a silicon-on-insulator process has a first semiconductor region and a second semiconductor region in a spaced relationship thereto A body structure is defined by a channel segment between the first semiconductor region and the second semiconductor region, and a first extension segment structurally contiguous with the channel segment. A shallow trench isolation structure surrounds the first semiconductor region, the second semiconductor region, and the body structure, with a first extension interface being defined between the shallow trench isolation structure and the first extension segment of the body structure to reduce leakage current flowing from the second semiconductor region to the first semiconductor region through a parasitic path of the body structure.

A structure for radiofrequency applications includes a high-resistivity support substrate having a front face defining a main plane, a charge-trapping layer disposed on the front face of the support substrate, a first dielectric layer disposed on the charge-trapping layer, an active layer disposed on the first dielectric layer, at least one buried electrode disposed above or in the charge-trapping layer. The buried electrode comprises a conductive layer and a second dielectric layer.

In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A source region and a drain region are disposed in the first semiconductor material layer and spaced apart. A gate electrode is disposed over the first semiconductor material layer between the source region and the drain region. A first doped region having a first doping type is disposed in the second semiconductor material layer, where the gate electrode directly overlies the first doped region. A second doped region having a second doping type different than the first doping type is disposed in the second semiconductor material layer, where the second doped region extends beneath the first doped region and contacts opposing sides of the first doped region.

A display device includes a substrate which includes a display area and a non-display area adjacent to the display area, a first planarization layer which is at least partially disposed in the display area, a second planarization layer which is disposed in the non-display area and is spaced apart from the first planarization layer, a contact unit disposed between the first planarization layer and the second planarization layer in the non-display area, and a cathode which extends from the display area to the non-display area to be electrically connected to the contact unit. Accordingly, the first planarization layer and the second planarization layer are spaced apart from each other so that a path through which moisture permeates into the display area through the second planarization layer may be blocked.

In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A source region and a drain region are disposed in the first semiconductor material layer and spaced apart. A gate electrode is disposed over the first semiconductor material layer between the source region and the drain region. A first doped region having a first doping type is disposed in the second semiconductor material layer, where the gate electrode directly overlies the first doped region. A second doped region having a second doping type different than the first doping type is disposed in the second semiconductor material layer, where the second doped region extends beneath the first doped region and contacts opposing sides of the first doped region.

An integrated electronic device is supported by a substrate of a silicon on insulator type. At least one transistor is formed in and on a semiconductor film of the substrate. The transistor includes a drain region and a source region of a first conductivity type and a substrate (body) region of a second conductivity type lying under a gate region. An extension region laterally continues the substrate (body) region beyond the source and drain regions and borders, in contact with, the source region through a border region having the first conductivity type. This supports formation of an electrical connection of the source region and the substrate (body) region.

The invention provides the guided design approach to optimize the device performance for a best area-efficient layout footprint in a single-leg MOS device that is based on any of the SOL SOS or SON technologies. The design methodology depends on new proprietaries device architectures that are also being claimed in this patent and that allow the implementations of the design equations in our methodology.