A power distribution device includes a substrate, a first chip, a first bump, a second bump and a first capacitor. The first chip is configured to receive a first reference voltage signal and a second reference voltage signal. The first bump is located between the substrate and the first chip, and configured to transmit the first reference voltage signal from the substrate to the first chip. The second bump is located between the substrate and the first chip, and configured to transmit the second reference voltage signal from the substrate to the first chip. The first capacitor is located above the substrate and below the first chip. A first terminal of the first capacitor is coupled to the first bump, and a second terminal of the first capacitor is coupled to the second bump. A power distribution system is also disclosed herein.

A display is created using “smart pixels.” A smart pixel is a pixel of a display that integrates the pixel pipeline as part of the pixel, rather than using separate integrated circuits. A smart pixel may be based on an integrated stack that includes light emitting elements, an external data contact for receiving digital data for that pixel, and also the pixel pipeline from the digital data to the light emitting elements.

Wafer processing techniques, or methods for forming semiconductor rides, are disclosed for fabricating plated pillar dies having die-level electromagnetic interference (EMI) shield layers. In embodiments, the method includes depositing a metallic seed layer over a semiconductor wafer and contacting die pads thereon. An electroplating process is then performed to compile plated pillars on the metallic seed layer and across the semiconductor wafer. Following electroplating, selected regions of the metallic seed layer are removed to produce electrical isolation gaps around a first pillar type, while leaving intact portions of the metallic seed layer to yield a wafer-level EMI shield layer. The semiconductor wafer is separated into singulated plated pillar dies, each including a die-level EMI shield layer and plated pillars of the first pillar type electrically isolated from the EMI shield layer.

A packaged electronic module for downhole applications, in particular in a petrochemical well or similar environment. The electronic module includes one or more electronic components located on each side of a substrate, where the one or more electronic components are attached to the substrate by means of glue.

A display is created using “smart pixels.” A smart pixel is a pixel of a display that integrates the pixel pipeline as part of the pixel, rather than using separate integrated circuits. A smart pixel may be based on an integrated stack that includes light emitting elements, an external data contact for receiving digital data for that pixel, and also the pixel pipeline from the digital data to the light emitting elements.

A semiconductor package includes a multilayer package substrate including a first layer including a first dielectric and first metal layer including a first metal trace and a second layer including a second dielectric layer. An integrated circuit (IC) die includes bond pads, with a bottom side of the IC die attached to the first metal trace. Metal pillars are through the second dielectric layer connecting to the first metal trace. A third layer on the second layer includes a third dielectric layer on the second layer extending to a bottom side of the semiconductor package, and a second metal layer including second metal traces including inner second metal traces connected to the bond pads and outer second metal traces over the metal pillars, and filled vias providing externally accessible contact pads that connect the second metal traces to a bottom side of the semiconductor package.

A semiconductor device includes a device carrier, a first semiconductor chip mounted on the device carrier and a second semiconductor chip mounted on the device carrier. Further, the semiconductor device includes a first contact clip bonded to a first electrode of the first semiconductor chip, a second contact clip bonded to a first electrode of the second semiconductor chip and an insulating connector configured to hold the first contact clip and the second contact clip together.

An isolated power transfer device includes a transformer formed in a multi-layer substrate of an integrated circuit package. A primary winding of the transformer is coupled to a first integrated circuit to form a DC/AC power converter and a secondary winding of the transformer is coupled to a second integrated circuit to form an AC/DC power converter. The first and second integrated circuits are electrically isolated from each other. The first integrated circuit includes a lightly doped drain MOSFET integrated with conventional CMOS devices and the second integrated circuit includes a Schottky diode integrated with conventional CMOS devices. The isolated power transfer device includes a capacitive channel for communication of information across an isolation barrier from the second integrated circuit to the first integrated circuit. Capacitors of the capacitive channel may be formed in the multi-layer substrate of the integrated circuit package.

There is disclosed herein clock generation circuitry, in particular rotary travelling wave oscillator circuitry. Such circuitry comprises a pair of signal lines connected together to form a dosed loop and arranged such that they define at least one transition section where both said lines in a first portion of the pair cross from one lateral side of both said lines in a second portion of the pair to the other lateral side of both said lines in the second portion of the pair.

Components may be placed on an active side of a wafer as part of wafer-level chip scale packaging (WLCSP) for use in electronic devices. Pad layouts for the components on an active side of a wafer may be passivation-defined by forming a conductive terminal over a first dielectric layer and a forming a passivating, second dielectric layer over the conductive terminal. Openings formed in the second dielectric layer define component contacts to the conductive terminal and circuitry on the wafer coupled to the conductive terminal. Trenches may be used between pairs of contact pads to further reduce issues resulting from short circuits and/or underfills. A conductive pad may further be deposited in the opening to form underbump metallization (UBM) for coupling the component to the wafer.