The present disclosure provides an electronic apparatus including a first surface, a second surface, a third surface, a plurality of conductive elements, and an encapsulant. The second surface is nonparallel to the first surface. The third surface is distinct from the first surface and the second surface. The plurality of conductive elements are exposed from the second surface. The encapsulant covers the third surface and exposes the first surface and the second surface.

An object of the present invention is to achieve both securing an insulation distance and securing a chip mounting area in a non-insulated power module. A non-insulated power module includes a plurality of die pads, a plurality of semiconductor chips mounted on upper surfaces of the plurality of die pads, and a package sealing the semiconductor chips, in which lower surfaces of the plurality of die pads are exposed from a lower surface of the package, on the lower surface of the package, first grooves are formed in areas between the plurality of die pads, and the plurality of die pads have a trapezoidal cross-sectional shape in the thickness direction, in which an area of an upper surface is larger than an area of the lower surface.

Packaged semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes a substrate and a plurality of integrated circuit dies coupled to the substrate. The device also includes a molding material disposed over the substrate between adjacent ones of the plurality of integrated circuit dies. A cap layer is disposed over the molding material and the plurality of integrated circuit dies, wherein the cap layer comprises an electrically conductive material that directly contacts the molding material and each of the plurality of integrated circuit dies.

An integrated circuit (IC) package is described. The IC package includes a die, having a pad layer structure on back-end-of-line layers on a substrate. The die also includes a metallization routing layer on the pad layer structure, and a first under bump metallization layer on the metallization routing layer. The IC package also includes a patterned seed layer on a surface of the die to contact the first under bump metallization layer. The IC package further includes a first package bump on the first under bump metallization layer.

A prepreg is used to fabricate a semiconductor package including a chip and a substrate to mount the chip thereon. The prepreg is in a semi-cured state. The substrate includes a cured product of the prepreg. The chip has: a first chip surface located opposite from the substrate; and a second chip surface located opposite from the first chip surface. The prepreg satisfies the relational expression: 0.9≤X.sub.2/X.sub.1≤1.0 (I), where X.sub.1 is a coefficient of thermal expansion of the first chip surface of the chip before the chip is mounted on the substrate, and X.sub.2 is a coefficient of thermal expansion of the first chip surface of the chip after the chip has been mounted on the substrate.

The present disclosure provides an electronic apparatus including a first surface, a second surface, a third surface, a plurality of conductive elements, and an encapsulant. The second surface is nonparallel to the first surface. The third surface is distinct from the first surface and the second surface. The plurality of conductive elements are exposed from the second surface. The encapsulant covers the third surface and exposes the first surface and the second surface.

An integrated circuit (IC) package is described. The IC package includes a die, having a pad layer structure on back-end-of-line layers on a substrate. The die also includes a metallization routing layer on the pad layer structure, and a first under bump metallization layer on the metallization routing layer. The IC package also includes a patterned seed layer on a surface of the die to contact the first under bump metallization layer. The IC package further includes a first package bump on the first under bump metallization layer.

An electronic device includes a main substrate, a semiconductor package structure and at least one heat pipe. The semiconductor package structure is electrically connected to the main substrate, and includes a die mounting portion, a semiconductor die and a cover structure. The semiconductor die is disposed on the die mounting portion. The cover structure covers the semiconductor die. The heat pipe contacts the cover structure for dissipating a heat generated by the semiconductor die.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a package substrate and a first integrated circuit (IC) chip disposed on the package substrate. The first IC chip includes first core circuitry, and first interface circuitry for communicating with the first core circuitry. A second IC chip is disposed on the package substrate and includes second core circuitry and second interface circuitry for communicating with the second core circuitry. The second interface circuitry exhibits a non-matching interface with respect to the first interface circuitry. Interface adapter circuitry couples to the first interface circuitry and the second interface circuitry to establish a common physical interface (PHY) for communicating between the first core circuitry and the second core circuitry.

A power module includes a recessed base plate having a hollow portion, at least one insulating substrate disposed in the hollow portion of the base plate, at least one semiconductor chip mounted on the at least one insulating substrate, and sealing resin for sealing a surface of the hollow portion side of the base plate, the at least one insulating substrate, and the at least one semiconductor chip.