A package structure includes an encapsulant, a patterned circuit structure, at least one electronic component and a shrinkage modifier. The patterned circuit structure is disposed on the encapsulant and includes a pad. The electronic component is disposed on the patterned circuit structure, and includes a bump electrically connected to the pad. The shrinkage modifier is encapsulated in the encapsulant and configured to reduce a relative displacement between the bump and the pad along a horizontal direction in an environment of temperature variation.

A component carrier includes a stack with at least one electrically conductive layer structure, at least one electrically insulating layer structure, a cavity delimited at a bottom side at least partially by a top side of a stepped metal structure of the at least one electrically conductive layer structure, and a component embedded in the cavity and arranged on the stepped metal structure. A bottom side of the stepped metal structure has a flat surface extending continuously along at least one horizontal direction.

Provided is a semiconductor package including a redistribution structure including at least one redistribution insulating layer and at least one redistribution pattern, at least one semiconductor chip located on the redistribution structure, and a molding layer located on the redistribution structure and covering the at least one semiconductor chip. The redistribution pattern includes a redistribution via passing through the redistribution insulating layer and extending in a first direction perpendicular to a top surface of the redistribution structure, and a redistribution line extending in a second direction parallel to the top surface of the redistribution structure. Inner side walls of the redistribution via have a certain inclination, and a difference between a thickness of a central portion of the redistribution line and a thickness of an edge of the redistribution line ranges from 1% to 10% of the thickness of the central portion of the redistribution line.

A semiconductor package includes a first semiconductor chip including a first semiconductor substrate, and a plurality of first through electrodes penetrating at least a portion of the first semiconductor substrate. A plurality of second semiconductors include a second semiconductor substrate, the plurality of second semiconductor chips being stacked on the first semiconductor chip. A plurality of bonding pads are arranged between the first semiconductor chip and the plurality of second semiconductor chips. A chip bonding insulating layer is arranged between the first semiconductor chip and the plurality of second semiconductor chips. At least one supporting dummy substrate is stacked on the plurality of second semiconductor chips and having a support bonding insulating layer arranged on a lower surface thereof.

Semiconductor assemblies including thermal management configurations for reducing heat transfer between overlapping devices and associated systems and methods are disclosed herein. A semiconductor assembly may comprise a first device and a second device with a thermally conductive layer, a thermal-insulator interposer, or a combination thereof disposed between the first and second devices. The thermally conductive layer and/or the thermal-insulator interposer may be configured to reduce heat transfer between the first and second devices.

Semiconductor assemblies including thermal management configurations for reducing heat transfer between overlapping devices and associated systems and methods are disclosed herein. A semiconductor assembly may comprise a first device and a second device with a thermally conductive layer, a thermal-insulator interposer, or a combination thereof disposed between the first and second devices. The thermally conductive layer and/or the thermal-insulator interposer may be configured to reduce heat transfer between the first and second devices.

The invention provides a circuit substrate and a package structure. The circuit substrate includes a molding compound having a chip-side surface and a solder ball-side surface opposite from the chip side surface. A first conductive bulk is formed embedded in the molding compound. The first conductive bulk has a first number of first chip-side bond pad surfaces and a second number of first solder ball-side surfaces exposed from the chip side surface and the ball-side surface, respectively. The width of the first conductive bulk is greater than the first width of the first chip-side bond pad surfaces and the second width of the first solder ball-side surfaces.

Electrical interconnect bridge technology is disclosed. An electrical interconnect bridge can include a bridge substrate formed of a mold compound material. The electrical interconnect bridge can also include a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and space (FLS) traces. In addition, the electrical interconnect bridge can include a via extending through the substrate and electrically coupling at least one of the FLS traces in one of the routing layers to at least one of the FLS traces in another of the routing layers.

Embodiments disclosed herein include a multi-die packages with an embedded bridge and a thinned surface. In an example, a multi-die interconnect structure includes a package substrate having a cavity. A bridge die is in the cavity of the package substrate, the bridge die including silicon. A dielectric material is over the package substrate, over the bridge die, and in the cavity. A plurality of conductive bond pads is on the dielectric material. The multi-die interconnect structure further includes a plurality of conductive pillars, individual ones of the plurality of conductive pillars on a corresponding one of the plurality of conductive bond pads. A solder resist material is on the dielectric material, on exposed portions of the plurality of conductive bond pads, and laterally surrounding the plurality of conductive pillars. The plurality of conductive pillars has a top surface above a top surface of the solder resist material.

A process for forming a semiconductor package. The process comprises forming a first leadframe strip mounted upon an adhesive tape. The first leadframe strip is at least partially encased in a first mold compound thereby forming a molded leadframe strip. At least one flip chip semiconductor device is mounted on the molded leadframe strip. The semiconductor device has conductive masses attached thereon to effectuate electrical contact between the semiconductor device and the molded leadframe. The conductive masses can be substantially spherical or cylindrical. Liquid encapsulant is dispensed on the semiconductor device to encapsulate the flip chip semiconductor device. A cavity is formed between the semiconductor device and the molded leadframe. The molded leadframe strip, the semiconductor device, and the conductive masses are at least partially encased in a second mold compound. The second mold compound can be molded so that a surface of the flip chip semiconductor device that is not attached to the molded leadframe is substantially exposed or molded to produce a globular form on the flip chip semiconductor device. The molded leadframe strip is singulated to form discrete semiconductor packages.